CHAPTER 4 BCU
Preliminary User’s Manual A14874EJ3V0UM
77
4.3 Programmable Chip Select Function
The VDCSZn signals corresponding to each bank of memory are set and the data area is subdivided into multiple
CSn areas according to the chip area select control registers 0 and 1 (CSC0 and CSC1) (n = 7 to 0). The CSC0 and
CSC1 registers can be read or written in 16-bit units.
When the VDCSZn signals for the same bank overlap due to the CSC0 and CSC1 register settings, the signal
prioritization is as follows.
•
VDCSZ0 > VDCSZ2 > VDCSZ1 > VDCSZ3
•
VDCSZ7 > VDCSZ5 > VDCSZ6 > VDCSZ4
Figure 4-1. Chip Area Select Control Register 0 (CSC0)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CSC0
CS
33
CS
32
CS
31
CS
30
CS
23
CS
22
CS
21
CS
20
CS
13
CS
12
CS
11
CS
10
CS
03
CS
02
CS
01
CS
00
Address
FFFFF060H
After reset
2C11H
Bit position
Bit name
Function
When each bit is set (1), the VDCSZn signal becomes active if the condition within
parentheses holds.
VDCSZn signal that becomes active
Bit name
64 MB mode
256 MB mode
CS00
VDCSZ0 (when accessing bank 0)
CS01
VDCSZ0 (when accessing bank 1)
CS02
VDCSZ0 (when accessing bank 2)
CS03
VDCSZ0 (when accessing bank 3)
CS10
VDCSZ1 (when accessing bank 0 or 1)
CS11
VDCSZ1 (when accessing bank 2 or 3)
CS12
VDCSZ1 (when accessing bank 4)
CS13
VDCSZ1 (when accessing bank 5)
VDCSZ1 (when accessing area 0)
(Same when each bit is cleared (0))
CS20
VDCSZ2 (when accessing bank 0)
CS21
VDCSZ2 (when accessing bank 1)
CS22
VDCSZ2 (when accessing bank 2)
CS23
VDCSZ2 (when accessing bank 3)
CS30
VDCSZ3 (when accessing bank 0, 1,
2, or 3)
CS31
VDCSZ3 (when accessing bank 4 or 5)
CS32
VDCSZ3 (when accessing bank 6)
CS33
VDCSZ3 (when accessing bank 7)
VDCSZ3 (when accessing area 1)
(Same when each bit is cleared (0))
15 to 0
CSn3 to
CSn0
Remark
n = 3 to 0
