CHAPTER 4 BCU
Preliminary User’s Manual A14874EJ3V0UM
78
Figure 4-2. Chip Area Select Control Register 1 (CSC1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CSC1
CS
43
CS
42
CS
41
CS
40
CS
53
CS
52
CS
51
CS
50
CS
63
CS
62
CS
61
CS
60
CS
73
CS
72
CS
71
CS
70
Address
FFFFF062H
After reset
2C11H
Bit position
Bit name
Function
When each bit is set (1), the VDCSZn signal becomes active if the condition within
parentheses holds.
VDCSZn signal that becomes active
Bit name
64 MB mode
256 MB mode
CS40
VDCSZ4 (when accessing bank 12,
13, 14, or 15)
CS41
VDCSZ4 (when accessing bank 10 or
11)
CS42
VDCSZ4 (when accessing bank 9)
CS43
VDCSZ4 (when accessing bank 8)
VDCSZ4 (when accessing area 2)
(Same when each bit is cleared (0))
CS50
VDCSZ5 (when accessing bank 15)
CS51
VDCSZ5 (when accessing bank 14)
CS52
VDCSZ5 (when accessing bank 13)
CS53
VDCSZ5 (when accessing bank 12)
CS60
VDCSZ6 (when accessing bank 14 or
15)
CS61
VDCSZ6 (when accessing bank 12 or
13)
CS62
VDCSZ6 (when accessing bank 11)
CS63
VDCSZ6 (when accessing bank 10)
VDCSZ6 (when accessing area 3)
(Same when each bit is cleared (0))
CS70
VDCSZ7 (when accessing bank 15)
CS71
VDCSZ7 (when accessing bank 14)
CS72
VDCSZ7 (when accessing bank 13)
CS73
VDCSZ7 (when accessing bank 12)
15 to 0
CSn3 to
CSn0
Remark
n = 4 to 7
