Preliminary User’s Manual A14874EJ3V0UM
15
LIST OF FIGURES (3/3)
Figure No. Title Page
7-33
Example of Two-Cycle Block Transfer Timing (Between External SRAMs Connected to NT85E500)............ 187
7-34
Example of Two-Cycle Single Transfer Timing
(from RAM Connected to VDB to SDRAM Connected to NT85E502) ............................................................. 189
7-35
Example of Two-Cycle Single Transfer Timing
(from SDRAM Connected to NT85E502 to RAM Connected to VDB) ............................................................. 191
7-36
Example of Flyby Single Transfer Timing (from External SRAM to External I/O Connected to NT85E500) ... 193
7-37
Example of Flyby Single-Step Transfer Timing
(from External SRAM to External I/O Connected to NT85E500) ..................................................................... 195
7-38
Example of Flyby Single-Step Transfer Timing
(from External I/O to External SRAM Connected to NT85E500) ..................................................................... 197
7-39
Example of Flyby Line Transfer Timing (from External SRAM to External I/O Connected to NT85E500)....... 199
7-40
Example of Flyby Block Transfer Timing (from External SRAM to External I/O Connected to NT85E500)..... 201
7-41
Example of Flyby Block Transfer Timing (from External I/O to External SRAM Connected to NT85E500)..... 203
8-1
Example of Non-Maskable Interrupt Request Acknowledgement Operation................................................... 210
8-2
Non-Maskable Interrupt Processing Format .................................................................................................... 212
8-3
RETI Instruction Processing Format................................................................................................................ 213
8-4
Maskable Interrupt Processing Format............................................................................................................ 215
8-5
RETI Instruction Processing Format................................................................................................................ 216
8-6
Servicing Example in Which Another Interrupt Request Is Issued During Interrupt Servicing............................. 218
8-7
Servicing Example for Simultaneously Issued Interrupt Requests .................................................................. 220
8-8
Interrupt Control Registers 0 to 63 (PIC0 to PIC63) ........................................................................................ 221
8-9
Interrupt Mask Registers 0 to 3 (IMR0 to IMR3) .............................................................................................. 222
8-10
In-Service Priority Register (ISPR) .................................................................................................................. 223
8-11
Program Status Word (PSW)........................................................................................................................... 224
8-12
Software Exception Processing Format .......................................................................................................... 225
8-13
RETI Instruction Processing Format................................................................................................................ 226
8-14
Illegal Opcode.................................................................................................................................................. 227
8-15
Exception Trap Processing Format ................................................................................................................. 228
8-16
Example of Pipeline Operation When Interrupt Request Is Acknowledged (Outline) ...................................... 229
9-1
Peripheral Macro Connection Example ........................................................................................................... 232
10-1
NB85E901 and NU85E Connection Example.................................................................................................. 243
10-2
N-Wire Type IE Connection............................................................................................................................. 244
10-3
IE Connector Pin Layout Diagram (Target System Side) ................................................................................ 244
10-4
Example of Recommended Circuit for IE Connection (NU85E + NB85E901) ................................................. 246
A-1
ROM Access Timing ........................................................................................................................................ 247
A-2
RAM Access Timing ........................................................................................................................................ 248
