CHAPTER 7 DMAC
Preliminary User’s Manual A14874EJ3V0UM
156
7.5.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)
These 16-bit registers are used to set the transfer counts for DMA channels n (n = 0 to 3). These registers
maintain the remaining transfer count during a DMA transfer.
Since they are two-stage FIFO-configuration buffer registers, the transfer count of a new DMA transfer can be set
during a DMA transfer (See
7.6 Next Address Setting Function
).
These registers are decremented by 1 for each transfer that is performed. Transfer ends when a borrow occurs.
These registers can be read or written in 16-bit units.
Note that in the case of line transfers, when the DBCn register is 0003H (4 transfers) this becomes one line
transfer. For a setting in which the transfer count cannot be divided by 4, the sections that can be line transferred are
(line) transferred first, then the remaining indivisible section is transferred as single transfers.
Figure 7-5. DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DBC0
BC
15
BC
14
BC
13
BC
12
BC
11
BC
10
BC
9
BC
8
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC
0
Address
FFFFF0C0H
After reset
Undefined
DBC1
BC
15
BC
14
BC
13
BC
12
BC
11
BC
10
BC
9
BC
8
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC
0
Address
FFFFF0C2H
After reset
Undefined
DBC2
BC
15
BC
14
BC
13
BC
12
BC
11
BC
10
BC
9
BC
8
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC
0
Address
FFFFF0C4H
After reset
Undefined
DBC3
BC
15
BC
14
BC
13
BC
12
BC
11
BC
10
BC
9
BC
8
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC
0
Address
FFFFF0C6H
After reset
Undefined
Bit position
Bit name
Function
Sets the transfer count. During a DMA transfer, the remaining transfer count is maintained.
DBCn
Status
0000H
Transfer 1 or remaining transfer count
0001H
Transfer 2 or remaining transfer count
…
…
FFFFH
Transfer 65,536 (2
16
) or remaining transfer count
15 to 0
BC15 to
BC0
Remark
n = 0 to 3
