CHAPTER 6 STBC
Preliminary User’s Manual A14874EJ3V0UM
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6.6 Clock Control in Software/Hardware STOP Mode
The NU85E and clock control circuit are connected as follows.
Figure 6-4. Connection of NU85E and Clock Control Circuit
VBCLK
Clock generator
(CG)
clk
X2
X1
STPRQ
STPAK
Memory controller
(MEMC)
Clock control circuit
Note
SWSTOPRQ
HWSTOPRQ
EN
NU85E
CGREL
Note
Design the clock control circuit as a user logic. Also, include a circuit for ensuring the oscillation
stabilization time (see
Figures 6-5
and
6-6
).
Caution In a system in which the MEMC is not connected to the NU85E, handle the STPAK pin in either
of the following ways.
••••
Always input a high level.
••••
Connect user logic that outputs a high level to the STPAK pin to the STPRQ output (high
level) of the NU85E.
If a high level is not input to the STPAK pin, the HWSTOPRQ and SWSTOPRQ signals do not
become active and shifting the STOP mode becomes impossible.
