Renesas NU85E, Preliminary User'S Manual

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CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual A14874EJ3V0UM
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Pin Name I/O Function
EVCLRIP Input ISPR clear input
EVINTAK Input Interrupt acknowledge input
EVINTRQ Output Interrupt request output
Peripheral
evaluation chip
mode pins
EVINTLV6 to EVINTLV0 Output Interrupt vector output
IFIROME Input ROM mapping enable input
IFIROB2 Input ROM area location setting input
IFIRA64 Input RAM area size selection input
IFIRA32 Input RAM area size selection input
IFIRA16 Input RAM area size selection input
IFIMAEN Input Misalign access setting input
IFID256 Input Data area setting input
IFINSZ1, IFINSZ0 Input VSB data bus size (initial value) selection input
IFIWRTH Input Data cache write-back/write-through mode selection input
IFIUNCH1 Input Data cache setting input
IFIUNCH0 Input Instruction cache setting input
PHEVA Input Peripheral evaluation chip mode setting input
IFIROBE Input
IFIROPR Input
IFIRASE Input
IFIRABE Input
IFIMODE3 Input
IFIMODE2 Input
IFIUSWE Input
Operation mode
setting pins
FCOMB Input
NEC reserved pins (input low level)
TBI39 to TBI0 Input Input test bus
TBO34 to TBO0 Output Output test bus
TEST Input Test bus control input
BUNRI Input Normal/test mode selection input
BUNRIOUT Output Test mode status output
PHTDO1, PHTDO0
Note
Input Peripheral macro test input
TESEN Output Peripheral macro test enable output
VPTCLK Output Peripheral macro test clock output
PHTDIN1, PHTDIN0 Output Peripheral macro test output
VPRESZ Output Peripheral macro reset output
PHTEST Output Peripheral test mode status output
TMODE1 Output Test mode selection output
TMODE0 Output
Test mode pins
TBREDZ Output
NEC reserved pins (leave open)
Note Connected internally to bus holder.