Renesas NU85E Preliminary User'S Manual Download Page 118

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CHAPTER 4 BCU

Preliminary User’s Manual A14874EJ3V0UM

116

4.9.7 Misalign access timing

The VSB access timing when misalign access is enabled (when a high level is input to the IFIMAEN pin) is shown

below.

Figure 4-18. Misalign Access Timing (1/2)

(a) Timing for access to even addresses

(Writing the 32-bit data “12345678H” to address “200002H”)

VMTTYP1, VMTTYP0

(Output)

VMLOCK (Output)

VMA27 to VMA0 (Output)

VMSTZ (Output)

VMBENZ3 to VMBENZ0

(Output)

VMCTYP2 to VMCTYP0

(Output)

VMSEQ2 to VMSEQ0

(Output)

VMSIZE1, VMSIZE0

(Output)

VDCSZ7 to VDCSZ0

(Output)

VBCLK (Input)

(1,0)

(0,0,1,1)

(1,1)

(1,0)

(1,1)

200002H

200004H

VMWRITE (Output)

(1,1,0,0)

(0,1,0)

(0,0,0)

(0,1)

VBDO31 to VBDO0

(Output)

VMWAIT (Input)

VMAHLD (Input)

VMLAST (Input)

Halfword write

56780000H

00001234H

VBDI31 to VBDI0

(Input)

Remarks 1.

O mark: Sampling timing

Arbitrary input level

The timing seen from the NU85E when the NU85E has the bus access right is shown.

Summary of Contents for NU85E

Page 1: ...ok over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electron...

Page 2: ...t for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas...

Page 3: ...Document No A14874EJ3V0UM00 3rd edition Date Published March 2002 N CP N Printed in Japan Preliminary User s Manual NU85E 32 Bit Microprocessor Core Hardware NU85E NU85EA...

Page 4: ...Preliminary User s Manual A14874EJ3V0UM 2 MEMO...

Page 5: ...te No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence c...

Page 6: ...ll be done under the full responsibility of the customer NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits softw...

Page 7: ...88 6130 800 729 9288 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Sin...

Page 8: ...0 12 34 5 5 6 7 5 8 2 6 12 34 8 3 9 4 6 1 2 8 3 6 1 2 8 3 2 2 2 5 3 8 2 2 7 42 8 2 2 1 5 42 2 1 9 3 42 2 2 3 4 3 3 6 12 42 5 9 2 2 5 7 0 5 2 3 2 6 12 9 4 9 4 2 42 0 1 7 4 9 9 93 9 3 A 6 8 4...

Page 9: ...anual is as follows NU85E User s Manual V850E1 User s Manual Hardware This manual Architecture Overview Register set CPU function Instruction format and instruction set Peripheral I O functions Interr...

Page 10: ...24 M mega 2 20 1 024 2 G giga 2 30 1 024 3 Data type Word 32 bits Halfword 16 bits Byte 8 bits Related Documents The related documents indicated in this publication may include preliminary versions Ho...

Page 11: ...4 DMAC pins 36 2 2 5 INTC pins 36 2 2 6 VFB pins 36 2 2 7 VDB pins 37 2 2 8 Instruction cache pins 38 2 2 9 Data cache pins 39 2 2 10 RCU pins 41 2 2 11 Peripheral evaluation chip mode pins 41 2 2 12...

Page 12: ...Related Register Setting Examples 91 4 9 Data Transfer Using VSB 94 4 9 1 Data transfer example 94 4 9 2 Control signals output by bus master 95 4 9 3 Read write timing 98 4 9 4 VSB read write timing...

Page 13: ...8 7 8 3 Line transfer mode 169 7 8 4 Block transfer mode 171 7 8 5 One time transfer when executing single transfers using DMARQn signal 172 7 9 Transfer Types 173 7 9 1 Two cycle transfer 173 7 9 2 F...

Page 14: ...de 232 9 4 Handling of Each Pin in Test Mode 233 CHAPTER 10 NB85E901 234 10 1 Symbol Diagram 234 10 2 Pin Functions 235 10 2 1 Pin function list 235 10 2 2 Pin functions 236 10 2 3 Recommended connect...

Page 15: ...al I O Area 84 4 6 Peripheral I O Area Select Control Register BPC 85 4 7 Bus Size Configuration Register BSC 86 4 8 Endian Configuration Register BEC 87 4 9 Word Data Little Endian Format Example 88...

Page 16: ...Disable Status Register DDIS 160 7 9 DMA Restart Register DRST 161 7 10 Buffer Register Configuration 162 7 11 DMAC Bus Cycle State Transition Diagram 165 7 12 Single Transfer Example 1 166 7 13 Sing...

Page 17: ...xternal SRAM Connected to NT85E500 203 8 1 Example of Non Maskable Interrupt Request Acknowledgement Operation 210 8 2 Non Maskable Interrupt Processing Format 212 8 3 RETI Instruction Processing Form...

Page 18: ...MCTYP0 Signals 95 4 3 VMBENZ3 to VMBENZ0 Signals 96 4 4 VMSIZE1 and VMSIZE0 Signals 96 4 5 VMSEQ2 to VMSEQ0 Signals 96 4 6 VMWAIT VMAHLD and VMLAST Signals 97 4 7 VBDC and VBDV Signals 97 5 1 Setting...

Page 19: ...ing the NU85E contains an on chip high speed hardware multiplier capable of executing 32 bit 32 bit operations 2 Bus interfaces The NU85E provides the following two types of bus interface for connecti...

Page 20: ...ogic UART Memory controller MEMC Test bus Clock control circuit Clock generator CG Instruction cache ROM RAM Data cache Debug controller ASIC External memory VDB VFB Remark VFB Dedicated bus for ROM d...

Page 21: ...rated bus 28 bit address Note 32 bit data bus Data I O separated bus 32 16 8 bit bus sizing function Bus hold function External wait function Endian switching function NPB NEC peripheral I O bus Addre...

Page 22: ...Preliminary User s Manual A14874EJ3V0UM 20 Power save function HALT mode Software STOP mode Hardware STOP mode RCU Note interface function Note The Run Control Unit RCU communicates using JTAG and exe...

Page 23: ...1 0 FCOMB PHEVA IFIWRTH IFIMODE3 in in in in in in in in in in in in in in in in in in in in out in out out out out in in in in in in out out out out out out CGREL SWSTOPRQ HWSTOPRQ DCSTOPZ STPRQ STP...

Page 24: ...I0 IDMASTP DMARQ3 to DMARQ0 DMTCO3 to DMTCO0 DMACTV3 to DMACTV0 IRAMA27 to IRAMA2 IRAMZ31 to IRAMZ0 IRAMEN IRAMWR3 to IRAMWR0 IRAMRWB IRAOZ31 to IRAOZ0 IRAMWT TEST BUNRI PHTDO1 PHTDO0 DMA control unit...

Page 25: ...dge BBR converts signals for the VSB to signals for the NPB The BBR sets up the wait insertion function and retry function for peripheral macros connected to the NPB See CHAPTER 5 BBR 4 STBC The stand...

Page 26: ...IT input VSWAIT output VBWAIT input output VMLAST input VSLAST output VBLAST input output VMAHLD input VSAHLD output VBAHLD input output VDSELPZ output VSSELPZ input VDSELPZ input output VSB master sl...

Page 27: ...utput Bus access right request output from internal bus master CPU DMAC VBDI31 to VBDI0 Input Data input from macro connected to VSB VBDO31 to VBDO0 Output Data output to macro connected to VSB VMA27...

Page 28: ...MC IDMASTP Input DMA transfer termination input DMARQ3 to DMARQ0 Input DMA transfer request input DMTCO3 to DMTCO0 Output Terminal count DMA transfer completion output DMAC pins DMACTV3 to DMACTV0 Out...

Page 29: ...nput to BCU IDDWRQ Input VSB write operation request input to BCU IDSEQ4 Input Read write operation type setting input IDSEQ2 Input Read write operation type setting input IRRSA Output VDB hold status...

Page 30: ...put Data cache setting input IFIUNCH0 Input Instruction cache setting input PHEVA Input Peripheral evaluation chip mode setting input IFIROBE Input IFIROPR Input IFIRASE Input IFIRABE Input IFIMODE3 I...

Page 31: ...access Even when an interrupt request occurs transfer to the PIFn flag of the PICn register is not performed while this signal outputs a high level n 0 to 63 7 VPUBENZ output This is the higher byte e...

Page 32: ...CPU 4 VBDI31 to VBDI0 input These pins constitute a data input bus for macro connected to VSB 5 VBDO31 to VBDO0 output These pins constitute a data output bus for macro connected to VSB 6 VMA27 to VM...

Page 33: ...E0 output These are pins that output the data transfer size when the NU85E has the bus access right Table 2 3 VMSIZE1 and VMSIZE0 Signals VMSIZE1 VMSIZE0 Data Transfer Size 0 0 Byte 8 bits 0 1 Halfwor...

Page 34: ...urst transfer continuous during burst transfer and single transfer at the end of burst transfer In the following cases VSB changes to burst transfer and the sequential status indicates continuous VSB...

Page 35: ...slave selection cannot be issued In such a case the slave device outputs a last response notifying the fact that the slave selection signal has changed to the bus master When there is a last response...

Page 36: ...CRESZ input This is the clock synchronized system reset input pin When the stable input clock rising edge is detected five times after a low level was input to this pin the pin statuses and internal s...

Page 37: ...input at least one clock after STOP mode is canceled and the oscillation stabilization time has been ensured it is not necessary to set CGREL input at the same time as VBCLK input 4 SWSTOPRQ output T...

Page 38: ...of the VBCLK signal 4 DMACTV3 to DMACTV0 output These are the DMA acknowledge output pins These pins become active high level output during a 2 cycle transfer VSB read or VSB write cycle or during a f...

Page 39: ...in synchronization with the falling edge of the VBCLK signal 5 IRAMWR3 to IRAMWR0 output These are the pins from which write enable signals are output to RAM They are high level active pins that indi...

Page 40: ...re output to the instruction cache 6 IBEDI31 to IBEDI0 output These pins constitute a bus from which data is output to the instruction cache Upon an instruction cache miss hit the data to be refilled...

Page 41: ...ion cache should be left open when using the instruction cache 2 2 9 Data cache pins 1 IDDARQ output This is the pin from which read write access requests are output to the data cache 2 IDAACK output...

Page 42: ...fetching the data to be read from the external memory this signal is output to indicate that a refill for the data cache is ready 8 IDRRDY input This is the pin to which read data ready signals are in...

Page 43: ...se pins 1 EVASTB input This is the address strobe input pin It is connected to the EPHASTB pin of the evaluation chip 2 EVDSTB input This is the data strobe input pin It is connected to the EPHDSTB pi...

Page 44: ...a low level is input to the IFIROB2 pin instruction processing begins after branching to the reset entry address of the ROM connected to VFB following the release of system reset If a high level is i...

Page 45: ...NSZ1 and IFINSZ0 Signals IFINSZ1 IFINSZ0 VSB Data Bus Size 0 0 32 bits 0 1 16 bits 1 0 8 bits 1 1 Setting prohibited Remark 0 low level input 1 high level input If the VSB data bus size is changed aft...

Page 46: ...put These are NEC reserved pins Always input low level signals 2 2 13 Test mode pins 1 TBI39 to TBI0 input These pins constitute an input test bus 2 TBO34 to TBO0 output These pins constitute an outpu...

Page 47: ...reset signal for the peripheral macros in normal operation mode as well as test mode 11 PHTEST output This is the pin from which signals indicating the peripheral test mode status are output 12 TMODE1...

Page 48: ...Output Leave open System control pins DCSTOPZ STPAK Input Input high level IDMASTP DMARQ3 to DMARQ0 Input Input low level DMAC pins DMTCO3 to DMTCO0 DMACTV3 to DMACTV0 Output Leave open INTC pins DCNM...

Page 49: ...V0 Output Leave open IFIROME IFIRA64 IFIRA32 IFIRA16 IFIMAEN IFID256 IFINSZ1 IFINSZ0 Input IFIROB2 IFIWRTH IFIUNCH0 Input Input low level or high level PHEVA IFIROBE IFIROPR IFIRASE IFIRABE IFIMODE3 I...

Page 50: ...DO31 to VBDO0 L Retained Retained Operates Undefined Operates VMA27 to VMA0 L Retained Retained Operates Undefined Operates VMTTYP1 VMTTYP0 L Retained Retained Operates Undefined Operates VMSTZ H Reta...

Page 51: ...ed Undefined Undefined Undefined Undefined Operates IRAMA27 to IRAMA2 Undefined Undefined Undefined Operates Undefined Operates IRAOZ31 to IRAOZ0 Undefined Undefined Undefined Operates Undefined Opera...

Page 52: ...ined Undefined DBO0 L Retained Retained Retained Undefined Undefined RCU pins DBB15 to DBB0 Undefined Retained Retained Retained Undefined Undefined EVIEN Undefined L L L Undefined Undefined EVOEN Und...

Page 53: ...ructions having long short format Three operand instructions Five stage pipeline structure with one clock pitch Register flag hazard interlock supported by hardware Memory space Program area 64 MB lin...

Page 54: ...15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 Element pointer EP r31 Link pointer LP PC Program counter 0 31 b System registers EIPC Register for saving status when interrupt occurs E...

Page 55: ...counter PC Holds instruction address during program execution Remark For detailed explanations of r1 r3 to r5 and r31 which are used by the assembler or C compiler refer to the C Compiler Package CA8...

Page 56: ...er 26 bits are valid and bits 31 to 26 are reserved for future function expansion fixed at 0 If a carry from bit 25 to bit 26 occurs it is ignored Also bit 0 is fixed at 0 and no branching to an odd a...

Page 57: ...able interrupt NMI is set in the higher 16 bits of this register FECC The exception code of an exception or maskable interrupt is set in the lower 16 bits EICC See Figure 3 3 No Yes 5 PSW Program stat...

Page 58: ...of the PC is fixed at 0 When setting a value in EIPC FEPC or CTPC set an even value bit 0 0 as long as there is no specific reason not to Figure 3 3 Interrupt Source Register ECR 31 16 15 0 ECR FECC...

Page 59: ...SAT Indicates that the calculation result of a saturated calculation processing instruction overflowed and the calculation result is saturated This flag which is called the saturation flag is set 1 w...

Page 60: ...CPU of the NU85E supports a linear address space with a maximum size of 4 GB Memory and I O are located in this address space memory mapped I O method Figure 3 5 Address Space Data area 4 GB linear 0...

Page 61: ...ripheral I O area 4 KB RAM area 4 12 28 or 60 KB 3FFFFFFH 3FFF000H 3FFEFFFH ROM areaNote 1 MB 00FFFFFH 0100000H 0000000H 64 MB External memory area Note When a low level signal is input to the IFIROME...

Page 62: ...viewed as 64 images in the 4 GB address space That is the same 64 MB physical address space is accessed regardless of the values of bits 31 to 26 of the CPU address Figure 3 7 Data Area 64 MB Mode Im...

Page 63: ...3FFF000H 3FFEFFFH Access prohibited area RAM area 4 12 28 or 60 KB External memory area ROM areaNote 1 1 MB Notes 1 When a low level signal is input to the IFIROME pin this is also used as the externa...

Page 64: ...exceptions This set of jump destination addresses is called the interrupt exception table and is located at address 00000000H and following When an interrupt exception request is acknowledged process...

Page 65: ...00090H INT1 00000210H INT25 00000390H INT49 000000A0H INT2 00000220H INT26 000003A0H INT50 000000B0H INT3 00000230H INT27 000003B0H INT51 000000C0H INT4 00000240H INT28 000003C0H INT52 000000D0H INT5...

Page 66: ...levels to the IFRA64 IFRA32 and IFRA16 pins Table 3 4 RAM Area Size Settings IFIRA64 IFIRA32 IFIRA16 RAM Area Size 0 0 0 4 KB 0 0 1 12 KB 0 1 Arbitrary 28 KB 1 Arbitrary Arbitrary 60 KB Remark 0 low...

Page 67: ...ing 60 KB cannot be set Example Memory map when 8 KB RAM is used RAM area xFFEFFFH xFFC000H xFFE000H xFFDFFFH The RAM area size is set to 12 KB The 8 KB from lower side addresses are RAM area 3 4 3 Pe...

Page 68: ...FFF000H xFFF05FH xFFF060H xFFEFFFH Reserved area xFFF7FFH xFFF800H xFFF7BFH xFFF7C0H User usable area xFFF100H xFFF0FFH Reserved area NU85E control register Reserved area Reserved area NU85E control r...

Page 69: ...address decoding after being allocated to the 4 KB area of xxxxx000H to xxxxxFFFH 2 The lowest bit of the address is not decoded Therefore when the register of an odd address 2n 1 address is byte acc...

Page 70: ...gister 1H DDA1H R W Undefined FFFFF090H DMA source address register 2L DSA2L R W Undefined FFFFF092H DMA source address register 2H DSA2H R W Undefined FFFFF094H DMA destination address register 2L DD...

Page 71: ...F116H Interrupt control register 3 PIC3 R W 47H FFFFF118H Interrupt control register 4 PIC4 R W 47H FFFFF11AH Interrupt control register 5 PIC5 R W 47H FFFFF11CH Interrupt control register 6 PIC6 R W...

Page 72: ...PIC40 R W 47H FFFFF162H Interrupt control register 41 PIC41 R W 47H FFFFF164H Interrupt control register 42 PIC42 R W 47H FFFFF166H Interrupt control register 43 PIC43 R W 47H FFFFF168H Interrupt con...

Page 73: ...ASC R W FFFFH FFFFF48CH Bus cycle period control register BCP R W 80H 00H FFFFF49AH Page ROM configuration register PRC R W 7000H FFFFF4A0H SDRAM configuration register 0 SCR0 R W 0000H FFFFF4A2H SDRA...

Page 74: ...active and tag initialization starts automatically The value changes to 0000H upon the completion of tag initialization 2 This value becomes 03H when the reset signal is active and tag initialization...

Page 75: ...cuit emulator 3 6 2 On chip debugging By connecting the RCU to the NU85E on chip debugging an on board debug function can be realized The CPU of the NU85E is equipped with a breakpoint function which...

Page 76: ...en consecutive clock falling edges Data transfer in 8 bit 16 bit or 32 bit units on a 32 bit bus by means of the bus size function Bus arbitration for a multi master system Programmable chip select fu...

Page 77: ...00H Bank 8 8 MB 27FFFFFH 2800000H Bank 9 8 MB 2FFFFFFH 3000000H Bank 10 4 MB 33FFFFFH 3400000H Bank 11 4 MB 37FFFFFH 3800000H Bank 12 2 MB 39FFFFFH 3A00000H Bank 13 2 MB 3BFFFFFH 3C00000H Bank 14 2 MB...

Page 78: ...FH C000000H F7FFFFFH F800000H F9FFFFFH FA00000H FBFFFFFH FC00000H FDFFFFFH FE00000H FFFFFFFH FFFF000H FFFFFFFH FFFEFFFH FE00000H 0100000H 01FFFFFH 00FFFFFH 0000000H External memory area External memor...

Page 79: ...s FFFFF060H After reset 2C11H Bit position Bit name Function When each bit is set 1 the VDCSZn signal becomes active if the condition within parentheses holds VDCSZn signal that becomes active Bit nam...

Page 80: ...13 14 or 15 CS41 VDCSZ4 when accessing bank 10 or 11 CS42 VDCSZ4 when accessing bank 9 CS43 VDCSZ4 when accessing bank 8 VDCSZ4 when accessing area 2 Same when each bit is cleared 0 CS50 VDCSZ5 when...

Page 81: ...accessing bank 3 VDCSZ3 when accessing bank 0 1 2 or 3 Notes 1 2 3 4 VDCSZ3 when accessing bank 4 or 5 Notes 5 6 VDCSZ3 when accessing bank 6 VDCSZ3 when accessing bank 7 Notes 1 Since the high prior...

Page 82: ...Notes 1 Since the high priority signal from the bit 2 setting VDCSZ7 corresponds to bank 13 only the setting in bank 12 becomes valid 2 Since the high priority signal from the bit 1 setting VDCSZ7 cor...

Page 83: ...Bank 5 4M VDCSZ1 Bank 6 8M VDCSZ3 Bank 7 8M VDCSZ3 Bank 8 8M VDCSZ4 Bank 9 8M VDCSZ4 Bank 10 4M VDCSZ6 Bank 11 4M VDCSZ6 Bank 12 2M VDCSZ6 Bank 13 2M VDCSZ7 Bank 14 2M VDCSZ7 Bank 15 2M VDCSZ5 CS7 are...

Page 84: ...ty signal from the bit 0 setting VDCSZ0 corresponds to bank 0 the setting becomes invalid Notes 3 Since the high priority signal from the bit 1 setting VDCSZ0 corresponds to bank 1 the setting becomes...

Page 85: ...unit bytes The values within brackets indicate the corresponding VDCSZn signal n 7 to 0 4 4 Programmable Peripheral I O Area Selection Function The NU85E has a 4 KB peripheral I O area that is alloca...

Page 86: ...FF000H 3FFEFFFH xxxnFFFH xxxm000H 0000000H Same area m yy00B Same area Same areaNote Peripheral I O area 4 KB 4 KB Programmable peripheral I O area 12 KB RAM area n yy11B m yy00B Note See Figure 3 8 D...

Page 87: ...hat is the same as the RAM area and that is located at address 3FFEFFFH and below See Figure 3 8 Data Area 256 MB Mode 3 If there are no peripheral macros connected to the NPB or user logic no program...

Page 88: ...Bit name Function Specifies the peripheral macro on the VSB that was located in the CSn area and the data bus size BSn1 BSn0 VSB data bus size 0 0 8 bits 0 1 16 bits 1 0 32 bits 1 1 Setting prohibited...

Page 89: ...format for these areas according to the BEC register is invalid Peripheral I O area ROM area RAM area The area that is the same as the RAM area and that is located at address 3FFEFFFH and below for 25...

Page 90: ...gger ID850 Only the memory window display supports the big endian format 2 When using the compiler CA850 a C language restrictions i The following restrictions are attached to variables configured in...

Page 91: ...mization section are mixed together The above optimization suppression options are therefore recommended 1 For global optimization section 1 bit set using bit or int i i 1 1 bit clear using bit and i...

Page 92: ...o the IFIUNCH0 or IFIUNCH1 pin In other cases the instruction data cache enabled setting is invalid even if the BHn0 BHn1 bit is set to 1 3 When using the data cache set this register after setting th...

Page 93: ...2 11 10 9 8 7 6 5 4 3 2 1 0 BPC Programmable peripheral I O area Can be accessed Programmable peripheral I O area starting address 2400000H b BSC register setting 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 15 14...

Page 94: ...Cache setting CSn area Addresses Banks VDCSZn signal VSB data bus size bits Endian format Instruction Data 0 0000000H to 03FFFFFH 0 1 VDCSZ0 32 Little endian No No 1 0800000H to 0FFFFFFH 4 5 VDCSZ1 32...

Page 95: ...000H Bank 4 0BFFFFFH 0C00000H Bank 5 0FFFFFFH 1000000H Bank 6 17FFFFFH 1800000H Bank 7 1FFFFFFH 2000000H Bank 9 2FFFFFFH 3000000H 33FFFFFH 3400000H Bank 11 37FFFFFH 3800000H Bank 12 39FFFFFH 3A00000H...

Page 96: ...according to the following prioritization TIC bus master 0 External circuit bus master 1 NU85E interior bus master 2 For example if a bus access right request VAREQ is generated from the TIC or an ex...

Page 97: ...nsfer type Table 4 1 VMTTYP1 and VMTTYP0 Signals VMTTYP1 VMTTYP0 Transfer Type 0 0 Address only transfer transfer without data processing 1 0 Non sequential transfer single transfer or burst transfer...

Page 98: ...ture function expansion Remark 0 low level 1 high level 5 Sequential status The bus master uses the VMSEQ2 to VMSEQ0 signals to indicate the burst transfer length when a burst transfer starts to indic...

Page 99: ...or future function expansion Remark 0 low level 1 high level Caution Once the VMAHLD signal becomes active 1 hold the active level 1 until the VMWAIT signal becomes inactive 0 It is not possible to re...

Page 100: ...edge of the VBCLK signal immediately after the active level VMAHLD was input and the bus master fetches samples the data in synchronization with the next falling edge of the VBCLK signal 2 Write timi...

Page 101: ...nput VMSTZ Output VMWAIT Input VMAHLD Input VMLAST Input VBDO31 to VBDO0 Output VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VMBSTR Output VBDC Ou...

Page 102: ...MAHLD Input VMLAST Input D 0 VBDI31 to VBDI0 Input VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VMBSTR Output VBDC Output VDCSZ7 to VDCSZ0 Output...

Page 103: ...TZ Output VMWAIT Input VMAHLD Input VMLAST Input D 0 VBDI31 to VBDI0 Input VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VMBSTR Output VBDC Output...

Page 104: ...to VMA0 Output VMWRITE Output Read Idle VMSTZ Output VMWAIT Input VMAHLD Input VMLAST Input D 0 VBDI31 to VBDI0 Input VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZ...

Page 105: ...nput VMSTZ Output VMWAIT Input VMAHLD Input VMLAST Input VBDI31 to VBDI0 Input VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VMBSTR Output VBDC Out...

Page 106: ...Output VMBSTR Output VBDC Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output 1 1 0 0 H xxH xxH 0 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 L D 9 D 11 D 12 Idle FFH 0 0 Idle FFH 0 0 1 1 1 1 VBCLK Inpu...

Page 107: ...Input VMSTZ Output VMWAIT Input VMAHLD Input VMLAST Input D 0 VBDI31 to VBDI0 Input VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VMBSTR Output VBD...

Page 108: ...EQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VMBSTR Output VBDC Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output H xxH 0 0 1 1 0 L Idle FFH 0 0 VBCLK Input 1 0 Word transfer Byte transfer Word transfer By...

Page 109: ...2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VMBSTR Output VBDC Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output H xxH 0 0 1 1 0 0 0 0 L Idle FFH 0 0 VBCLK Input 1 0 Word transfer Byte transfer Word transfe...

Page 110: ...VMSEQ0 Output VMSIZE1 VMSIZE0 Output VMBSTR Output VBDC Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output H A 1 A 3 A 2 0 0 0 L Idle FFH 0 0 VBCLK Input A 0 A 4 A 6 A 5 Word transfer Byte transfer Word tr...

Page 111: ...MSEQ0 Output VMSIZE1 VMSIZE0 Output VMBSTR Output VBDC Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output H 1 0 0 0 0 L Idle FFH 0 0 VBCLK Input Word transfer Byte transfer Word transfer Byte transfer Idle...

Page 112: ...t VMSIZE1 VMSIZE0 Output VMBSTR Output VBDC Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output H A 1 A 3 A 2 1 0 0 0 1 L Idle FFH 0 0 A 0 A 4 A 6 A 5 Word transfer Byte transfer Idle 0 1 Halfword transfer...

Page 113: ...t VMAHLD Input VMLAST Input VBDI31 to VBDI0 Input VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VBDC Output VDCSZ7 to VDCSZ0 Output DI31 to DI0 Inp...

Page 114: ...MBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VBDC Output VDCSZ7 to VDCSZ0 Output DI31 to DI0 Input Note FFH 1 0 1 0 1 1 1 1 1 1 VBCLK Input VBDO31 to VBDO0 Ou...

Page 115: ...Output VMSTZ Output VBDI31 to VBDI0 Input VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output 0 0 DCRESZ Input 0 0...

Page 116: ...s bus master to other master device M2 is as follows 1 M1 which operates as the bus master inputs a VSB access right request signal VAREQ from M2 another master device 2 The bus arbiter within M1 goes...

Page 117: ...MSEQ2 to VMSEQ0 VMSTZ VMBSTR VBDC Output Ctrl 2 Ctrl 3 VDCSZ7 to VDCSZ0 Output CS 2 CS 3 VBDO31 to VBDO0 Output VMLOCK Output VMTTYP1 VMTTYP0 Output VDSELPZ Output 1 1 0 0 VMA27 to VMA0 Output A 1 Ctr...

Page 118: ...0 Output VMLOCK Output VMA27 to VMA0 Output VMSTZ Output VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VDCSZ7 to VDCSZ0 Output VBCLK Input 1 0 0 0...

Page 119: ...TYP0 Output VMSEQ2 to VMSEQ0 Output VMSIZE1 VMSIZE0 Output VDCSZ7 to VDCSZ0 Output VBCLK Input 1 0 0 1 1 1 1 1 1 0 1 1 200003H 200004H VMWRITE Output H 1 1 0 0 0 1 0 0 0 0 VBDI31 to VBDI0 Input VMWAIT...

Page 120: ...between the VSB and NPB The BBR sets up the following functions for peripheral macros that are connected to the NPB Wait insertion function Retry function Figure 5 1 NPB Connection Overview BCU BBR P...

Page 121: ...0 VPWRITE Address decoder VPDO15 to VPDO0 VPSTB VPUBENZ VPLOCK VPRETR VPCS VPDW15 to VPDW0 VPDR15 to VPDR0 Peripheral macro 1 VPCS VPDW15 to VPDW0 VPDR15 to VPDR0 Peripheral macro 2 NU85E VPAnNote to...

Page 122: ...trol register BPC Figure 5 3 Peripheral I O Area and Programmable Peripheral I O Area a 64 MB mode b 256 MB mode n yy11B Peripheral I O area 4 KB 4 KB Programmable peripheral I O area 12 KB FFFFFFFH F...

Page 123: ...Cautions 1 In 64 MB mode if the programmable peripheral I O area overlaps the following areas the programmable peripheral I O area becomes ineffective Peripheral I O area ROM area RAM area 2 In 256 M...

Page 124: ...8000000H BFFFFFFH C000000H F7FFFFFH F800000H Bank 12 F9FFFFFH FA00000H Bank 13 FBFFFFFH FC00000H Bank 14 FDFFFFFH FE00000H Bank 15 FFFFFFFH Area 2 Area 3 Programmable peripheral I Oarea 2402FFFH 2400...

Page 125: ...on the internal system clock VBCLK The VSWC register can be read or written in 8 bit or 1 bit units Figure 5 6 NPB Strobe Wait Control Register VSWC 1 2 7 6 5 4 3 2 1 0 VSWC 0 SUWL2 SUWL1 SUWL0 0 VSW...

Page 126: ...ck Setup wait VBCLK Input 1 clock 1 5 clock Be sure to set values for the setup wait and VPSTB wait lengths at each operation frequency that are the same as or greater than the number of waits shown i...

Page 127: ...high level signal is being input to the VPRETR and VPDACT pins at the falling edge of the VPSTB signal the VPSTB signal rises again and the read or write operation is repeated Figure 5 7 Retry Functi...

Page 128: ...I O register Each one of these figures shows the timing as seen from the NU85E when the NU85E has the bus access right Remark O mark Sampling timing A x Arbitrary address output from the VPA13 to VPA...

Page 129: ...Output VPRETR Input VPLOCK Output VPUBENZ Output VPSTB Output VPDI15 to VPDI8 Input VPDO7 to VPDO0 Output VPDI7 to VPDI0 Input Figure 5 10 Timing of Byte Access to Even Address A 0 A 1 Read cycle Wri...

Page 130: ...PDO15 to VPDO0 Output VPDI15 to VPDI0 Input Remark The VPLOCK signal becomes active during a read operation Figure 5 12 Retry Timing Write VPA13 to VPA0 Output Address VPWRITE Output VPSTB Output VPUB...

Page 131: ...0 Output Address VPWRITE Output VPSTB Output VPUBENZ Output VPLOCK Output VPRETR Input VPDI15 to VPDI0 Input VPDACT Input Data Data Remark If the VPRETR and VPDACT signals are high level at the fallin...

Page 132: ...Output VSAHLD Output VSLAST Output VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSIZE1 VMSIZE0 Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output VPSTB Output VPWRITE Output VPUBENZ Output VPDO15 t...

Page 133: ...AIT Output VSAHLD Output VSLAST Output VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSIZE1 VMSIZE0 Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output VPSTB Output VPWRITE Output VPUBENZ Output VPDO...

Page 134: ...ut VSAHLD Output VSLAST Output VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSIZE1 VMSIZE0 Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output VPSTB Output VPWRITE Output VPUBENZ Output VPDO15 to VP...

Page 135: ...put VSAHLD Output VSLAST Output VMBENZ3 to VMBENZ0 Output VMCTYP2 to VMCTYP0 Output VMSIZE1 VMSIZE0 Output VDCSZ7 to VDCSZ0 Output VDSELPZ Output VPSTB Output VPWRITE Output VPUBENZ Output VPDI15 to V...

Page 136: ...ENZ0 Output VMCTYP2 to VMCTYP0 Output VMSIZE1 VMSIZE0 Output VPSTB Output VDCSZ7 to VDCSZ0 Output VPUBENZ Output 0 0 1 0 1 0 FFH 1 1 0 0 VBCLK Input VBDO31 to VBDO0 Output VPWRITE Output VPLOCK Output...

Page 137: ...M 135 5 5 Precautions NPB access from external master to NU85E BBR does not provide a bus sizing function Therefore NPB access from the external bus master of the VSB to the NU85E as a slave must be e...

Page 138: ...T mode and normal operation mode 2 Software STOP mode This mode which stops the overall system by stopping the external clock generator is set by means of a PSC register setting The system enters an u...

Page 139: ...MI2M Masks non maskable interrupt requests NMI2 from the DCNMI2 pin Note 0 Enables NMI2 requests 1 Disables NMI2 requests 6 NMI1M Masks non maskable interrupt requests NMI1 from the DCNMI1 pin Note 0...

Page 140: ...MD r20 PRCMD 01FCH 3 st b r11 PSC r20 PSC 01FEH 4 nop nop nop nop nop 2 1 mov 0x02 r11 movea 0xF1FCH r0 r20 movea 0xF1FEH r0 r21 2 st b r11 0x0 r20 r20 FFFFF1FCH PRCMD 3 st b r11 0x0 r21 r21 FFFFF1FEH...

Page 141: ...so that the application system is not halted unexpectedly due to erroneous program execution Only the first write operation to the PSC register is valid after a registration code arbitrary 8 bit data...

Page 142: ...nterrupt request HALT mode is canceled by a non maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority The following table shows the operation performed aft...

Page 143: ...equest an unmasked maskable interrupt request or the input of a DCRESZ signal a Cancellation by interrupt request Software STOP mode is canceled by a non maskable interrupt request not masked by the P...

Page 144: ...ware STOP mode is canceled and the interrupt request is not acknowledged pending Non maskable interrupt Non maskable interrupt request High Software STOP mode is canceled and the interrupt request is...

Page 145: ...ignal which controls the external clock generator does not become active because the slave device connected to the locked bus may require clock supply Consequently clock is not stopped and the NU85E w...

Page 146: ...EL Note Design the clock control circuit as a user logic Also include a circuit for ensuring the oscillation stabilization time see Figures 6 5 and 6 6 Caution In a system in which the MEMC is not con...

Page 147: ...put a non maskable interrupt request NMIm unmasked maskable interrupt request INTn or the DCRESZ signal m 2 to 0 n 63 to 0 2 Set the software STOP mode request signal SWSTOPRQ to inactive low level an...

Page 148: ...CGREL Input Oscillation stabilization time 1 clock or more Remarks 1 The DCNMIm and INTn inputs are detected at the rising edge and the interrupt request is held in the CPU 2 m 2 to 0 n 63 to 0 b Whe...

Page 149: ...ol circuit b When canceling hardware STOP mode 1 Input the DCRESZ signal or the inactive level high level of the DCSTOPZ signal 2 Set the hardware STOP mode request signal HWSTOPRQ to inactive low lev...

Page 150: ...ut CGREL Input 1 clock or more Oscillation stabilization time b When hardware STOP mode is canceled by DCRESZ input clk VBCLK Input STPRQ Output STPAK Input HWSTOPRQ Output DCSTOPZ Input CGREL Input O...

Page 151: ...r modes Single transfer mode Single step transfer mode Line transfer mode four bus cycle transfer mode in 2 cycle transfer the operation from read to write is repeated four times Block transfer mode T...

Page 152: ...rol register DCHCn DMA source address register DSAnH DSAnL DMA transfer count register DBCn DMA addressing control register DADCn Count control Channel control Address control Data control RAM Memory...

Page 153: ...ransfer Remark Yes Transfer enabled No Transfer disabled VSB External memory or peripheral macro on the VSB NPB Peripheral macro on the NPB RAM RAM directly connected to the VDB 2 Wait function Table...

Page 154: ...ure 7 1 DMA Source Address Registers 0H to 3H DSA0H to DSA3H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSA0H IR 0 0 0 SA 27 SA 26 SA 25 SA 24 SA 23 SA 22 SA 21 SA 20 SA 19 SA 18 SA 17 SA 16 Address FFFFF0...

Page 155: ...A 14 SA 13 SA 12 SA 11 SA 10 SA 9 SA 8 SA 7 SA 6 SA 5 SA 4 SA 3 SA 2 SA 1 SA 0 Address FFFFF088H After reset Undefined DSA2L SA 15 SA 14 SA 13 SA 12 SA 11 SA 10 SA 9 SA 8 SA 7 SA 6 SA 5 SA 4 SA 3 SA 2...

Page 156: ...H DDA0H to DDA3H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDA0H IR 0 0 0 DA 27 DA 26 DA 25 DA 24 DA 23 DA 22 DA 21 DA 20 DA 19 DA 18 DA 17 DA 16 Address FFFFF086H After reset Undefined DDA1H IR 0 0 0 DA...

Page 157: ...DDA1L DA 15 DA 14 DA 13 DA 12 DA 11 DA 10 DA 9 DA 8 DA 7 DA 6 DA 5 DA 4 DA 3 DA 2 DA 1 DA 0 Address FFFFF08CH After reset Undefined DDA2L DA 15 DA 14 DA 13 DA 12 DA 11 DA 10 DA 9 DA 8 DA 7 DA 6 DA 5 D...

Page 158: ...are line transferred first then the remaining indivisible section is transferred as single transfers Figure 7 5 DMA Transfer Count Registers 0 to 3 DBC0 to DBC3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D...

Page 159: ...et 0000H DADC3 DS 1 DS 0 0 0 0 0 0 0 SAD 1 SAD 0 DAD 1 DAD 0 TM1 TM0 TTYPTDIR Address FFFFF0D6H After reset 0000H Bit position Bit name Function Sets the transfer data size for a DMA transfer DS1 DS0...

Page 160: ...0 1 Decrement 1 0 Fixed 1 1 Setting prohibited 5 4 DAD1 DAD0 Sets the transfer mode used for DMA transfers TM1 TM0 Transfer mode 0 0 Single transfer mode 0 1 Single step transfer mode 1 0 Line transf...

Page 161: ...DMA transfer has ended 3 MLEn If this bit is set 1 when a terminal count is output the ENn bit is not cleared 0 and the status in which DMA transfer is enabled continues Also the next DMA transfer re...

Page 162: ...status register DDIS This register maintains the contents of the ENn bit of the DCHCn register when an IDMASTP signal is input n 0 to 3 This register is read only in 8 bit or 1 bit units Figure 7 8 DM...

Page 163: ...it of the corresponding DMA channel This register can be read or written in 8 bit or 1 bit units Figure 7 9 DMA Restart Register DRST 7 6 5 4 3 2 1 0 DRST 0 0 0 0 EN3 EN2 EN1 EN0 Address FFFFF0F2H Aft...

Page 164: ...terminal count signal DMTCOn is output these registers are automatically rewritten with the values that had just been set before the signal is output Therefore if a new DMA transfer is set for these...

Page 165: ...or the last state of a 2 cycle transfer read In the last T2R state read data is sampled After the read data is sampled the DMAC always transitions to the T1W state 6 T2RI state This is a DMA transfer...

Page 166: ...ue flyby transfers If the next transfer is executed in block transfer mode the DMAC moves to the T1FH state after the T2FH state In other modes if a wait has occurred the DMAC transitions to the T1FHI...

Page 167: ...er s Manual A14874EJ3V0UM 165 7 7 2 DMAC bus cycle state transitions Figure 7 11 DMAC Bus Cycle State Transition Diagram a Two cycle transfer T1W T2RI T1R T0 TI T1RI T2R T1WI T2W TE TI b Flyby transfe...

Page 168: ...transfer after the bus is released for the CPU is a transfer based on the newly generated lower priority DMA transfer request Figures 7 12 to 7 15 show examples for single transfer Figure 7 12 Single...

Page 169: ...hannel 3 terminal count Note Note Note Note The bus is always released Figure 7 15 shows a single transfer mode example in which two or more lower priority DMA transfer requests are generated within o...

Page 170: ...s the higher priority DMA transfer request always takes precedence Figures 7 16 and 7 17 show single step transfer mode examples Figure 7 16 Single Step Transfer Example 1 DMA1 CPU CPU CPU CPU CPU CPU...

Page 171: ...d and the next DMA transfer after the bus is released for the CPU is a transfer based on the newly generated lower priority DMA transfer request Figures 7 18 to 7 21 show examples for line transfer Fi...

Page 172: ...nsfer Example 3 DMA3 CPU DMA0 CPU DMA0 DMA0 DMA0 DMA3 CPU DMA3 DMA3 DMARQ3 Input DMA0 Note Note DMARQ0 Input DMA0 DMA0 DMA channel 0 terminal count CPU DMA3 DMA3 DMA3 CPU DMA3 DMA channel 3 terminal c...

Page 173: ...is prohibited to insert a CPU bus cycle during a block transfer bus mastership can be transferred even during a block transfer in response to a request by the external bus master including SDRAM refre...

Page 174: ...DMACTVn signal does not become active during transfer to RAM so if the transfer destination write cycle is RAM the timing when the write cycle ends cannot be determined n 3 to 0 When executing a sing...

Page 175: ...n a 2 cycle transfer data is transferred in 2 cycles a read cycle transfer source to DMAC and a write cycle DMAC to transfer destination In the first cycle the transfer source address is output to rea...

Page 176: ...respectively Signals indicating DMA flyby transfer 1 1 1 are also output from the VMCTYP2 to VMCTYP0 pins Only the data bus on the memory side of the memory controller is used for data so the VBDI31...

Page 177: ...If the ENn bit of the DCHCn register is set to 1 and the TCn bit is set to 0 the DMARQn signal becomes active in TI state n 3 to 0 If the DMARQn signal becomes active in TI state the DMAC moves to T0...

Page 178: ...channel n terminal count CPU DMARQn Input DMTCOn Output Remark n 3 to 0 During 2 cycle transfer the signal becomes active for one clock at the beginning of the last write cycle During flyby transfer t...

Page 179: ...sfer mode when the ENn bit is set 1 the next DMA transfer request is acknowledged and DMA transfer begins Caution To forcibly interrupt DMA transfer and stop the next transfer from occurring the IDMAS...

Page 180: ...inished in a block transfer using the VSB it is not possible to exercise a forcible termination during this transfer Figure 7 29 DMA Transfer Forcible Termination Example 1 2 a Block transfer using DM...

Page 181: ...1 transfer is forcibly terminated and the bus is released EN1 bit 1 TC1 bit 0 EN1 bit 0 TC1 bit 1 DSA1 DDA1 DBC1 DADC1 DCHC1 Set register CPU DSA1 DDA1 DBC1 Set register DCHC1 INIT1 bit 1 Set register...

Page 182: ...f the timing of 2 cycle transfers between RAM connected to the VDB and SDRAM connected to the MEMC NT85E502 Remarks 1 The levels of the broken line portions of the VMCTYP2 to VMCTYP0 VMSEQ2 to VMSEQ0...

Page 183: ...to DI0 Input Note RDZ Output Note A25 to A0 Output Note VMSEQ2 to VMSEQ0 Output VBCLK Input VBDC Output DMARQn Input DMACTVn Output DMTCOn Output WRZ3 to WRZ0 Output Note CSZ7 to CSZ0 Output Note VMLO...

Page 184: ...ansfer between external SRAMs connected to the NT85E500 The settings of the registers in this figure are as follows Register settings DBCn register 0002H 3 transfers ASC register Note 0000H No address...

Page 185: ...te RDZ Output Note A25 to A0 Output Note VMSEQ2 to VMSEQ0 Output VBCLK Input VBDC Output DMARQn Input DMACTVn Output DMTCOn Output WRZ3 to WRZ0 Output Note CSZ7 to CSZ0 Output Note VMLOCK Output 2H 3H...

Page 186: ...between the external SRAMs connected to the NT85E500 The settings of the registers in this figure are as follows Register settings DBCn register 0007H 8 transfers ASC register Note 0000H No address s...

Page 187: ...DMACTVn Output DMTCOn Output WRZ3 to WRZ0 Output Note CSZ7 to CSZ0 Output Note VMLOCK Output 2H 2H 0H 0H FH FH FH L L FH 1st 2 cycle line transfer 0H 0H FH FFH 3H 2H 3H 2H 0H 3H 2H 3H 2nd 2H 0H 3H 2H...

Page 188: ...r between the external SRAMs connected to the NT85E500 The settings of the registers in this figure are as follows Register settings DBCn register 0006H 7 transfers ASC register Note 0000H No address...

Page 189: ...utput 0H FH L L FH 1st 2 cycle block transfer 7 times 0H FH FFH 2H 2H 0H 3H 2H 3H 2nd 4th 0H 0H 6H 6H 6H 6H 6H 0H 0H 0H 0H 0H 0H 2H 2H 2H 2H 2H 6H 6H 6H 0H 0H 2H 2H 6H 6H 0H 0H 2H 2H 2H FBH FFH FBH FB...

Page 190: ...to the VDB to SDRAM connected to the NT85E502 The settings of the registers in this figure are as follows Register settings DBCn register 0001H 2 transfers SCRn register Note 2062H CAS latency 2 numb...

Page 191: ...Output DI31 to DI0 Input Note2 SDRASZ Output Note2 A25 to A0 Output Note2 VMSEQ2 to VMSEQ0 Output VBCLK Input SDCLK Output Note1 DMARQn Input DMACTVn Output DMTCOn Output SDWEZ Output Note2 CSZ7 to C...

Page 192: ...ed to the NT85E502 to RAM connected to the VDB The settings of the registers in this figure are as follows Register settings DBCn register 0001H 2 transfers SCRn register Note 2062H CAS latency 2 numb...

Page 193: ...utput DI31 to DI0 Input Note2 SDRASZ Output Note2 A25 to A0 Output Note2 VMSEQ2 to VMSEQ0 Output VBCLK Input SDCLK Output Note1 VBDC Output DMARQn Input DMACTVn Output DMTCOn Output SDWEZ Output Note2...

Page 194: ...ted by means of a setting in the NT85E500 s BCC register TW state This is a wait state inserted by means of a setting in the NT85E500 s DWC0 register Remarks 1 The levels of the broken line portions o...

Page 195: ...SIZE1 VMSIZE0 Output VDCSZ7 to VDCSZ0 Output DI31 to DI0 Input Note RDZ Output Note A25 to A0 Output Note VMSEQ2 to VMSEQ0 Output VBCLK Input VBDC Output DMARQn Input DMACTVn Output DMTCOn Output WRZ3...

Page 196: ...m external SRAM to external I O connected to the NT85E500 The settings of the registers in this figure are as follows Register settings DBCn register 0001H 2 transfers ASC register Note FFEFH CS2 addr...

Page 197: ...VMSIZE1 VMSIZE0 Output VDCSZ7 to VDCSZ0 Output DI31 to DI0 Input Note RDZ Output Note A25 to A0 Output Note VMSEQ2 to VMSEQ0 Output VBCLK Input VBDC Output DMARQn Input DMACTVn Output DMTCOn Output WR...

Page 198: ...m external I O to external SRAM connected to the NT85E500 The settings of the registers in this figure are as follows Register settings DBCn register 0001H 2 transfers ASC register Note FFEFH CS2 addr...

Page 199: ...VMSIZE0 Output VDCSZ7 to VDCSZ0 Output DI31 to DI0 Input Note RDZ Output Note A25 to A0 Output Note VMSEQ2 to VMSEQ0 Output VBCLK Input VBDC Output DMARQn Input DMACTVn Output DMTCOn Output WRZ3 to W...

Page 200: ...om external SRAM to external I O connected to the NT85E500 The settings of the registers in this figure are as follows Register settings DBCn register 0007H 8 transfers ASC register Note 0000H No addr...

Page 201: ...TCOn Output WRZ3toWRZ0 Output Note CSZ7toCSZ0 Output Note VMLOCK Output 0H FH FFH L L FH FFH 1st T1 T2 T3 L 7H FBH IORDZ Output Note IOWRZ Output Note H 2H 2H 3H FBH 2nd T1 T2 T3 0H FH 0H 0H 2H FFH FF...

Page 202: ...rom external SRAM to external I O connected to the NT85E500 The settings of the registers in this figure are as follows Register settings DBCn register 0007H 8 transfers ASC register Note 0000H No add...

Page 203: ...utput DI31 to DI0 Input Note RDZ Output Note A25 to A0 Output Note VMSEQ2 to VMSEQ0 Output VBCLK Input VBDC Output DMARQn Input DMACTVn Output DMTCOn Output WRZ3 to WRZ0 Output Note CSZ7 to CSZ0 Outpu...

Page 204: ...rom external I O to external SRAM connected to the NT85E500 The settings of the registers in this figure are as follows Register settings DBCn register 0007H 8 transfers ASC register Note 0000H No add...

Page 205: ...ote RDZ Output Note A25 to A0 Output Note VMSEQ2 to VMSEQ0 Output VBCLK Input VBDC Output DMARQn Input DMACTVn Output DMTCOn Output WRZ3 to WRZ0 Output Note CSZ7 to CSZ0 Output Note VMLOCK Output 0H F...

Page 206: ...the rising edge of the IRAMEN signal for transfer from RAM to VSB n 3 to 0 3 5 clocks Access to RAM connected to VDB 1 clock In the case of external memory access these depend on the connected MEMC a...

Page 207: ...nal must retain the request until the DMACTVn signal becomes active If the DMARQn signal is made inactive before the DMACTVn signal becomes active DMA transfer may not be executed n 3 to 0 7 VMLOCK si...

Page 208: ...ption trap 1 source illegal opcode exception These interrupt exception sources are listed in Table 8 1 Table 8 1 Interrupt Exception List 1 3 Interrupt Exception Source Type Classifi cation Name Contr...

Page 209: ...PC Interrupt INT22 PIC22 INT22 input 22 01E0H 000001E0H nextPC Interrupt INT23 PIC23 INT23 input 23 01F0H 000001F0H nextPC Interrupt INT24 PIC24 INT24 input 24 0200H 00000200H nextPC Interrupt INT25 P...

Page 210: ...Interrupt INT59 PIC59 INT59 input 59 0430H 00000430H nextPC Interrupt INT60 PIC60 INT60 input 60 0440H 00000440H nextPC Interrupt INT61 PIC61 INT61 input 61 0450H 00000450H nextPC Interrupt INT62 PIC6...

Page 211: ...W s NP bit is cleared 0 while NMI0 is being serviced the newly generated NMI1 request is executed NMI0 servicing is halted 3 If an NMI2 request is generated while NMI0 is being serviced The new NMI2 r...

Page 212: ...simultaneously Main routine NMI1 servicing System reset NMI0 and NMI2 requests generated simultaneously Main routine NMI0 and NMI2 requests generated simultaneously NMI2 servicing Systemreset NMI1 and...

Page 213: ...P 0 set before NMI1 request Main routine NMI0 request NMI1 request NMI0 servicing NMI1 servicing System reset NP 0 Held pending NMI2 request generated during NMI0 servicing Main routine NMI0 request N...

Page 214: ...the higher halfword FECC of the ECR 4 Set the NP and ID bits of the PSW and clear the EP bit 5 Set the handler address for the non maskable interrupt in the PC and shift control Figure 8 2 shows the...

Page 215: ...t of the RETI instruction Figure 8 3 RETI Instruction Processing Format 0 PSW EP PC EIPC PSW EIPSW 1 PSW NP 0 1 PC FEPC PSW FEPSW RETI instruction Original processing restored Caution If the PSW EP bi...

Page 216: ...wledged interrupt request specified by the interrupt control register is enabled Interrupts having the same priority level cannot be nested However the following processing is required for multiple in...

Page 217: ...of interrupt currently processed No Yes Priority higher than that of other interrupt request No Yes Highest default priority of interrupt requests with same priority No Yes PSW NP 0 PSW ID 1 1 EIPC Re...

Page 218: ...C address and PSW status Figure 8 5 shows the processing format of the RETI instruction Figure 8 5 RETI Instruction Processing Format 0 PSW EP PC EIPC PSW EIPSW 1 PSW NP 0 1 PC FEPC PSW FEPSW RETI ins...

Page 219: ...ies if multiple interrupts having the same priority level according to the PICn register are generated at the same time the interrupts are serviced according to the priorities default priorities that...

Page 220: ...cing of e Servicing of f Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e EI Interrupt request g level 1 Servicing of g Servicing of h In...

Page 221: ...Interrupt request s level 1 Servicing of u Servicing of s Servicing of t Interrupt request t level 2Note 1 Interrupt request u level 2Note 2 Interrupt requests m and n are held pending because servic...

Page 222: ...st c level 1 Servicing of c Servicing of b Servicing of a Main routine EI Default priority a b c Interrupt requests b and c are acknowledged first according to their priorities Because the priorities...

Page 223: ...o After reset 47H FFFFF18EH Bit position Bit name Function 7 PIFn This is the interrupt request flag 0 No interrupt request issued 1 Interrupt request issued When the interrupt request is acknowledged...

Page 224: ...1 bit units Figure 8 9 Interrupt Mask Registers 0 to 3 IMR0 to IMR3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IMR0 PMK 15 PMK 14 PMK 13 PMK 12 PMK 11 PMK 10 PMK 9 PMK 8 PMK 7 PMK 6 PMK 5 PMK 4 PMK 3 PMK...

Page 225: ...ority among the bits that are set 1 within the ISPR register is automatically cleared 0 However it is not cleared 0 when control returns from non maskable interrupt service or exception processing Thi...

Page 226: ...ID Indicates whether maskable interrupt service is enabled or disabled 0 The acknowledgement of maskable interrupts is enabled 1 The acknowledgement of maskable interrupts is disabled pending This bit...

Page 227: ...interrupt source 4 Set the EP and ID bits of the PSW 5 Set the handler address 00000040H or 00000050H for the software exception in the PC and shift control Figure 8 12 shows the processing format of...

Page 228: ...ddress and PSW status Figure 8 13 shows the processing format of the RETI instruction Figure 8 13 RETI Instruction Processing Format 0 PSW EP PC EIPC PSW EIPSW 1 0 1 PC FEPC PSW FEPSW PSW NP Original...

Page 229: ...he sub opcode of the instruction to be executed next is an illegal opcode 8 5 1 Illegal opcode The illegal opcode which has a 32 bit long instruction format is defined as an arbitrary opcode in which...

Page 230: ...NP EP and ID bits of the PSW 4 Set the handler address 00000060H for the exception trap in the PC and shift control Figure 8 15 shows the processing format of exception trap processing Figure 8 15 Exc...

Page 231: ...EX MEM WB Instruction 1 IFx IDx INT1 INT2 INT3 INT4 IF ID EX Instruction 2 Interrupt acknowledgement operation Instruction first instruction of interrupt service routine Remark INT1 to INT4 Interrupt...

Page 232: ...standby test mode Table 9 1 List of Test Mode Settings BUNRI Pin Input Level TEST Pin Input Level Mode Low level Arbitrary Normal mode High level Low level Standby test mode High level High level Unit...

Page 233: ...o the TBI39 to TBI0 pins is ignored and the TBO34 to TBO0 pins are set to high impedance 9 1 3 BUNRIOUT pin The level input to the BUNRI pin is output as is from the BUNRIOUT pin To support the test b...

Page 234: ...the NU85E the NPB peripheral macro and the MEMC is shown below Figure 9 1 Peripheral Macro Connection Example NU85E VPRESZ VPTCLK PHTDIN0 PHTDIN1 PHTDO0 PHTDO1 PHTEST TMODE0 TMODE1 TBREDZ TBI39 TBI0...

Page 235: ...put low level PHTDINn Output Connect to the PHTDINn pin of the NT85E500 VPRESZ Output Connect to the VPRESZ pin of the NT85E500 NT85E502 Connect to the VPRESZ pin VPTCLK Output Connect to the VPTCLK p...

Page 236: ...B85E901 with an N Wire type in circuit emulator N Wire type IE makes it possible to perform on chip debugging on the NU85E 10 1 Symbol Diagram out in out in in in out in DBINT RESETZ STOPZ NMI 2 0 VAR...

Page 237: ...ut NEC reserved pin input low level System control pins DCOP13 to DCOP0 Output NEC reserved pin leave open VBCLK Input System clock input DBI5 to DBI0 Output Debug control output DBO14 to DBO0 Input D...

Page 238: ...U reset input pin The RCU is reset asynchronously when a low level is input c DMS input This is the pin to which the debug mode selection is input from the N Wire type IE d DDI input This is the pin t...

Page 239: ...rol I O pins Connect them to pins DBB15 to DBB0 on the NU85E e TMODE1 input This is the test mode selection input pin Connect it to the TMODE1 pin on the NU85E f VBWAIT input This is the wait response...

Page 240: ...al wait request output pin b STPAK input This is the STOP mode request acknowledge input pin Input the STPAK signal from the memory controller 5 Test mode pins a BUNRI input This is the input pin for...

Page 241: ...TOPZ WAITZ Input Input a high level NMI2 to NMI0 VAREQ ROMTYPE Input Input a low level System control pins DCOP13 to DCOP0 Output Leave open VBCLK DBO14 to DBO0 TMODE1 VBTCLK Input DBI5 to DBI0 Output...

Page 242: ...s H Operates H Operates H Operates H Operates H Operates DBI0 L H L H L H L H L H L H DBB15 to DBB0 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained O...

Page 243: ...perates H Operates H Operates H Operates H Operates H Operates DBINT L Operates L Operates L Operates L Operates L Operates L Operates ROMTYPE L L L L L L Note When a low level is input to the DCRESZ...

Page 244: ...ed 6 Debug interrupt interface The forcible break function can be executed by inputting a high level to the DBINT pin Remark It is also possible to release the HALT software STOP and hardware STOP mod...

Page 245: ...MI0 DCNMI0 Note 3 TMODE1 TMODE1 VBWAIT VMWAIT RESETZ STOPZ NMI2 NMI1 NMI0 DCRESZ DCSTOPZ DCNMI1 DCNMI2 DCNMI0 BUNRI DCWAITZ Note 6 VAREQ Note 6 WAITZ Note 5 VAREQ WAITZ ROMTYPE DCOP13 DCOP0 WAITZ STPA...

Page 246: ...0 MC NW A Connector for IE connection 8830E 026 170S L product of KEL Corporation 10 5 1 IE connector target system side Figure 10 3 shows the pin layout of the IE connector target system side and Tab...

Page 247: ...3 input A6 TRCEND Input Trace data end input A7 DDI Output Debug serial interface data output A8 DCK Output Debug serial interface clock output A9 DMS Output Debug serial interface transfer mode selec...

Page 248: ...Notes 1 Make the clock pattern length as short as possible and shield it by surrounding it with GND Avoid exceeding a pattern length of 100 mm 2 Make the pattern length as short as possible Avoid exc...

Page 249: ...Input IROMEN Output IROMA19 to IROMA2 Output IROMZ31 to IROMZ0 Input A0 A1 Hold A3 D0 D1 A2 A4 D2 Note D3 A5 D4 Note Data should be retained from when the IROMEN output becomes high level until the V...

Page 250: ...AMZ31 to IRAMZ0 Input IRAMEN Output A0 A1 A2 D0 D1 D2 Remarks 1 Ax Arbitrary address Dx Data corresponding to address Ax 2 RAM data sampling timing b Write timing VBCLK Input IRAMRWB Output IRAMA27 to...

Page 251: ...155 DA27 to DA16 154 DAD1 DAD0 158 DADC0 to DADC3 157 Data area 60 Data transfer using VSB 94 DBB15 to DBB0 41 DBC0 to DBC3 156 DBI5 to DBI0 41 DBO14 to DBO0 41 DBPC 55 DBPSW 55 DCHC0 to DCHC3 159 DCN...

Page 252: ...BEA2 38 IBEDI31 to IBEDI0 38 ID 57 224 IDAACK 39 IDDARQ 39 IDDRDY 40 IDDRRQ 39 IDDWRQ 39 IDEA27 to IDEA0 40 IDED31 to IDED0 40 IDES 40 IDHUM 40 IDMASTP 36 IDRETR 40 IDRRDY 40 IDSEQ2 39 IDSEQ4 39 IDUNC...

Page 253: ...on 244 O On chip debugging 73 OV 57 P PA13 to PA00 85 121 PA15 85 121 PC 53 54 Periods when interrupts cannot be acknowledged 229 Peripheral I O area 65 Peripheral I O area select control register 85...

Page 254: ...159 TDIR 158 TE state 164 Terminal count output when DMA transfer is complete 176 TESEN 44 TEST 44 Test function 230 TI state 163 TM1 TM0 158 TMODE0 45 TMODE1 45 Transfer objects 151 TTYP 158 Two cycl...

Page 255: ...APPENDIX B INDEX Preliminary User s Manual A14874EJ3V0UM 253 VSLOCK 31 VSSELPZ 33 VSSTZ 30 VSWAIT 33 VSWC 123 VSWL2 to VSWL0 124 VSWRITE 31 W Wait insertion function 123 Z Z 57...

Page 256: ...14 b Example of timing of halfword data write to NPB peripheral macro programmable peripheral I O area p 134 Modification of Figure 5 15 NPB Write Timing Example of Timing of Data Write to CSC0 and CS...

Page 257: ...886 2 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 6503 2...

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