Preliminary User’s Manual A14874EJ3V0UM
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CHAPTER 3 CPU
The CPU of the NU85E, which is based on a RISC architecture, executes almost all instructions in one clock cycle
due to its five-stage pipeline control.
3.1 Features
•
Advanced 32-bit architecture for embedded control
• Number of instructions: 83
• Number of 32-bit general-purpose registers: 32
• Load/store instructions having long/short format
• Three-operand instructions
• Five-stage pipeline structure with one-clock pitch
• Register/flag hazard interlock supported by hardware
• Memory space
Program area: 64 MB linear address space
Data area: 4 GB linear address space
•
Instruction set suited to various application fields
• Saturated calculation instructions
• Bit manipulation instructions (set, clear, not, test)
• Multiplication can be performed in 1 or 2 clocks due to on-chip hardware multiplier
16 bits
×
16 bits
→
32 bits
32 bits
×
32 bits
→
32 bits or 64 bits
•
RCU interface function
