Renesas NU85E, Preliminary User'S Manual

Page: 70 / 257

CHAPTER 3 CPU
Preliminary User’s Manual A14874EJ3V0UM
68
3.5.1 NU85E control registers
(1/4)
Bit Units for Manipulation Address Register Name Symbol R/W
1 Bit 8 Bits 16 Bits
After Reset
FFFFF060H Chip area select control register 0 CSC0 R/W
√
2C11H
FFFFF062H Chip area select control register 1 CSC1 R/W
√
2C11H
FFFFF064H Peripheral I/O area select control register BPC R/W
√
0000H
FFFFF066H Bus size configuration register BSC R/W
√
0000H/
5555H/
AAAAH
FFFFF068H Endian configuration register BEC R/W
√
0000H
FFFFF06AH Cache configuration register BHC R/W
√
0000H
FFFFF06EH NPB strobe wait control register VSWC R/W
√ √
77H
FFFFF080H DMA source address register 0L DSA0L R/W
√
Undefined
FFFFF082H DMA source address register 0H DSA0H R/W
√
Undefined
FFFFF084H DMA destination address register 0L DDA0L R/W
√
Undefined
FFFFF086H DMA destination address register 0H DDA0H R/W
√
Undefined
FFFFF088H DMA source address register 1L DSA1L R/W
√
Undefined
FFFFF08AH DMA source address register 1H DSA1H R/W
√
Undefined
FFFFF08CH DMA destination address register 1L DDA1L R/W
√
Undefined
FFFFF08EH DMA destination address register 1H DDA1H R/W
√
Undefined
FFFFF090H DMA source address register 2L DSA2L R/W
√
Undefined
FFFFF092H DMA source address register 2H DSA2H R/W
√
Undefined
FFFFF094H DMA destination address register 2L DDA2L R/W
√
Undefined
FFFFF096H DMA destination address register 2H DDA2H R/W
√
Undefined
FFFFF098H DMA source address register 3L DSA3L R/W
√
Undefined
FFFFF09AH DMA source address register 3H DSA3H R/W
√
Undefined
FFFFF09CH DMA destination address register 3L DDA3L R/W
√
Undefined
FFFFF09EH DMA destination address register 3H DDA3H R/W
√
Undefined
FFFFF0C0H DMA transfer count register 0 DBC0 R/W
√
Undefined
FFFFF0C2H DMA transfer count register 1 DBC1 R/W
√
Undefined
FFFFF0C4H DMA transfer count register 2 DBC2 R/W
√
Undefined
FFFFF0C6H DMA transfer count register 3 DBC3 R/W
√
Undefined
FFFFF0D0H DMA addressing control register 0 DADC0 R/W
√
0000H
FFFFF0D2H DMA addressing control register 1 DADC1 R/W
√
0000H
FFFFF0D4H DMA addressing control register 2 DADC2 R/W
√
0000H
FFFFF0D6H DMA addressing control register 3 DADC3 R/W
√
0000H
FFFFF0E0H DMA channel control register 0 DCHC0 R/W
√ √
00H
FFFFF0E2H DMA channel control register 1 DCHC1 R/W
√ √
00H
FFFFF0E4H DMA channel control register 2 DCHC2 R/W
√ √
00H
FFFFF0E6H DMA channel control register 3 DCHC3 R/W
√ √
00H
FFFFF0F0H DMA disable status register DDIS R
√ √
00H