CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual A14874EJ3V0UM
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(13) VMCTYP2 to VMCTYP0 (output)
These are pins that output the current bus cycle status when the NU85E has the bus access right.
Table 2-4. VMCTYP2 to VMCTYP0 Signals
VMCTYP2
VMCTYP1
VMCTYP0
Bus Cycle Status
0
0
0
Opcode fetch
0
0
1
Data access
0
1
0
Misalign access
Note
0
1
1
Read modify write access
1
0
0
Opcode fetch of jump address due to branch instruction
1
1
0
DMA 2-cycle transfer
1
1
1
DMA flyby transfer
1
0
1
(Reserved for future function expansion)
Note
Output only when a high level is input to the IFIMAEN pin (misalign access enabled).
Remark
0: low-level 1: high-level
(14) VMSEQ2 to VMSEQ0 (output)
These are pins that output the sequential status indicating the transfer size during burst transfer when the
NU85E has bus access right.
These pins indicate “burst transfer length” at the start of burst transfer, “continuous” during burst transfer, and
“single transfer” at the end of burst transfer.
In the following cases, VSB changes to burst transfer and the sequential status indicates “continuous”.
•
VSB is 8 bits wide and 16-/32-bit data transfer was performed
•
VSB is 16 bits wide and 32-bit data transfer was performed
•
Refill from instruction/data cache
•
32-bit data transfer to peripheral macro connected to NPB (16-bit data bus width)
Table 2-5. VMSEQ2 to VMSEQ0 Signals
VMSEQ2
VMSEQ1
VMSEQ0
Sequential Status
0
0
0
Single transfer
0
0
1
Continuous (indicates that the next transfer address is related to the current
transfer address)
Note
0
1
0
Continuous 4 times (burst transfer length: 4)
0
1
1
Continuous 8 times (burst transfer length: 8)
1
0
0
Continuous 16 times (burst transfer length: 16)
1
0
1
Continuous 32 times (burst transfer length: 32)
1
1
0
Continuous 64 times (burst transfer length: 64)
1
1
1
Continuous 128 times (burst transfer length: 128)
Note
This is output during continuous 2 times, or continuous 4, 8, 16, 32, 64, or 128 times transfer.
Remark
0: low-level 1: high-level
