CHAPTER 5 BBR
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5.4 NPB Read/Write Timing
Figure 5-8 to Figure 5-13 show the basic read/write timing of NPB, Figure 5-14 shows a timing example for
read/write access to a bus slave connected to the NU85E and NPB, and Figure 5-15 shows a timing example of write
access to a peripheral I/O register. Each one of these figures shows the timing as seen from the NU85E when the
NU85E has the bus access right.
Remark
O mark: Sampling timing
A.x:
Arbitrary address output from the VPA13 to VPA0 pins
D.x:
I/O data for address “A.x”
:
Signal in undefined state (for output signal), arbitrary level (for input signal)
Figure 5-8. Halfword Access Timing
VPWRITE (Output)
VPA13 to VPA0
(Output)
VPDO15 to VPDO0
(Output)
VPRETR (Input)
D.0
A.0
A.1
Read cycle
Write cycle
VPLOCK (Output)
VPUBENZ (Output)
L
VPSTB (Output)
VPDI15 to VPDI0
(Input)
D.1
