CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual A14874EJ3V0UM
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Pin Name
I/O
Function
VSLOCK
Input
Bus lock input
VSWAIT
Output
Wait response output
VSLAST
Output
Last response output
VSAHLD
Output
Address hold response output
VSSELPZ
Input
Peripheral I/O area access status input
VBDC
Output
Data input (VBDI31 to VBDI0) control output
VBDV
Output
Data output (VBDO31 to VBDO0) control output
VSB pins
VDCSZ7 to VDCSZ0
Output
Chip select output
DCRESZ
Input
System reset input
VBCLK
Input
Internal system clock input
CGREL
Input
Clock generator release input
SWSTOPRQ
Output
Software STOP mode request output to clock generator
HWSTOPRQ
Output
Hardware STOP mode request output to clock generator
DCSTOPZ
Input
Hardware STOP mode request input
STPRQ
Output
Hardware/software STOP mode request output to MEMC
System control
pins
STPAK
Input
Acknowledge input for STPRQ input of MEMC
IDMASTP
Input
DMA transfer termination input
DMARQ3 to DMARQ0
Input
DMA transfer request input
DMTCO3 to DMTCO0
Output
Terminal count (DMA transfer completion) output
DMAC pins
DMACTV3 to DMACTV0
Output
DMA acknowledge output
DCNMI2 to DCNMI0
Input
Non-maskable interrupt request (NMI) input
INTC pins
INT63 to INT0
Input
Maskable interrupt request input
IROMA19 to IROMA2
Output
ROM address output
IROMZ31 to IROMZ0
Input
ROM data input
IROMEN
Output
ROM access enable output
IROMWT
Input
ROM wait input
IROMCS
Output
IROMIA
Output
VFB pins
IROMAE
Output
NEC reserved pins (leave open)
IRAMA27 to IRAMA2
Output
RAM address output
IRAMZ31 to IRAMZ0
Input
RAM data input
IRAOZ31 to IRAOZ0
Output
RAM data output
IRAMEN
Output
RAM access enable output
IRAMWR3 to IRAMWR0
Output
RAM write enable output
IRAMRWB
Output
RAM read/write status output
VDB pins
IRAMWT
Input
RAM wait input
IBDRRQ
Input
Fetch request input from instruction cache
IBEA25 to IBEA2
Input
Fetch address input from instruction cache
Instruction
cache pins
IBAACK
Output
Address acknowledge output to instruction cache
