CHAPTER 3 CPU
Preliminary User’s Manual A14874EJ3V0UM
71
(4/4)
Bit Units for Manipulation
Address
Register Name
Symbol
R/W
1 Bit
8 Bits
16 Bits
After Reset
FFFFF18EH
Interrupt control register 63
PIC63
R/W
√
√
47H
FFFFF1FAH
In-service priority register
ISPR
R
√
√
00H
FFFFF1FCH
Command register
PRCMD
W
√
Undefined
FFFFF1FEH
Power save control register
PSC
R/W
√
√
00H
3.5.2 Memory controller (MEMC) control registers
Bit Units for Manipulation
Address
Register Name
Symbol
R/W
1 Bit
8 Bits
16 Bits
After Reset
FFFFF480H
Bus cycle type configuration register 0
BCT0
R/W
√
8888H/0000H
FFFFF482H
Bus cycle type configuration register 1
BCT1
R/W
√
8888H/0000H
FFFFF484H
Data wait control register 0
DWC0
R/W
√
7777H
FFFFF486H
Data wait control register 1
DWC1
R/W
√
7777H
FFFFF488H
Bus cycle control register
BCC
R/W
√
FFFFH
FFFFF48AH
Address setting wait control register
ASC
R/W
√
FFFFH
FFFFF48CH
Bus cycle period control register
BCP
R/W
√
√
80H/00H
FFFFF49AH
Page ROM configuration register
PRC
R/W
√
7000H
FFFFF4A0H
SDRAM configuration register 0
SCR0
R/W
√
0000H
FFFFF4A2H
SDRAM refresh control register 0
RFS0
R/W
√
0000H
FFFFF4A4H
SDRAM configuration register 1
SCR1
R/W
√
0000H
FFFFF4A6H
SDRAM refresh control register 1
RFS1
R/W
√
0000H
FFFFF4A8H
SDRAM configuration register 2
SCR2
R/W
√
0000H
FFFFF4AAH
SDRAM refresh control register 2
RFS2
R/W
√
0000H
FFFFF4ACH
SDRAM configuration register 3
SCR3
R/W
√
0000H
FFFFF4AEH
SDRAM refresh control register 3
RFS3
R/W
√
0000H
FFFFF4B0H
SDRAM configuration register 4
SCR4
R/W
√
0000H
FFFFF4B2H
SDRAM refresh control register 4
RFS4
R/W
√
0000H
FFFFF4B4H
SDRAM configuration register 5
SCR5
R/W
√
0000H
FFFFF4B6H
SDRAM refresh control register 5
RFS5
R/W
√
0000H
FFFFF4B8H
SDRAM configuration register 6
SCR6
R/W
√
0000H
FFFFF4BAH
SDRAM refresh control register 6
RFS6
R/W
√
0000H
FFFFF4BCH
SDRAM configuration register 7
SCR7
R/W
√
0000H
FFFFF4BEH
SDRAM refresh control register 7
RFS7
R/W
√
0000H
