CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Preliminary User’s Manual U19014EJ1V0UD
181
7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
The following four registers are used to control 8-bit timer/event counters 50 and 51.
•
Timer clock selection register 5n (TCL5n)
•
8-bit timer mode control register 5n (TMC5n)
•
Port mode register 1 (PM1) or port mode register 3 (PM3)
•
Port register 1 (P1) or port register 3 (P3)
(1) Timer clock selection register 5n (TCL5n)
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input.
TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets TCL5n to 00H.
Remark
n = 0, 1
Figure 7-5. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH After reset: 00H R/W
Symbol
7 6 5 4 3 2 1 0
TCL50 0 0 0 0 0
TCL502
TCL501
TCL500
Count clock selection
TCL502 TCL501 TCL500
f
PRS
=
12 MHz
f
PRS
=
16 MHz
0
0
0
TI50 pin falling edge
0
0
1
TI50 pin rising edge
0 1 0
f
PRS
12 MHz
16 MHz
0 1 1
f
PRS
/2
6 MHz
8 MHz
1 0 0
f
PRS
/2
2
3 MHz
4 MHz
1 0 1
f
PRS
/2
6
187.5 kHz
250 kHz
1 1 0
f
PRS
/2
8
46.88 kHz
62.5 kHz
1 1 1
f
PRS
/2
13
1.46 kHz
1.95 kHz
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.
Remark
f
PRS
: Peripheral hardware clock frequency
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