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NEC mPD78F0730, Preliminary User'S Manual


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CHAPTER  21   INSTRUCTION  SET 

Preliminary User’s Manual  U19014EJ1V0UD 

480 

 

Clocks Flag 

Instruction 

Group 

Mnemonic Operands Bytes

Note 1

Note 2 

Operation 

Z AC CY

CY, saddr.bit 

3 

6 

7 

CY 

←

 CY 

∧

 (saddr.bit) 

 

 

×

CY, sfr.bit 

3 

−

 

7 CY 

←

 CY 

∧

 sfr.bit 

 

 

×

CY, A.bit 

2 

4 

−

 

CY 

←

 CY 

∧

 A.bit 

 

 

×

CY, PSW.bit 

3 

−

 

7 CY 

←

 CY 

∧

 PSW.bit 

 

 

×

AND1 

CY, [HL].bit 

2 

6 

7 

CY 

←

 CY 

∧

 (HL).bit 

 

 

×

CY, saddr.bit 

3 

6 

7 

CY 

←

 CY 

∨

 (saddr.bit) 

 

 

×

CY, sfr.bit 

3 

−

 

7 CY 

←

 CY 

∨

 sfr.bit 

 

 

×

CY, A.bit 

2 

4 

−

 

CY 

←

 CY 

∨

 A.bit 

 

 

×

CY, PSW.bit 

3 

−

 

7 CY 

←

 CY 

∨

 PSW.bit 

 

 

×

OR1 

CY, [HL].bit 

2 

6 

7 

CY 

←

 CY 

∨

 (HL).bit 

 

 

×

CY, saddr.bit 

3 

6 

7 

CY 

←

 CY 

∨

 (saddr.bit) 

 

 

×

CY, sfr.bit 

3 

−

 

7 CY 

←

 CY 

∨

 sfr.bit 

 

 

×

CY, A.bit 

2 

4 

−

 

CY 

←

 CY 

∨

 A.bit 

 

 

×

CY, PSW. bit 

3 

−

 

7 CY 

←

 CY 

∨

 PSW.bit 

 

 

×

XOR1 

CY, [HL].bit 

2 

6 

7 

CY 

←

 CY 

∨

 (HL).bit 

 

 

×

saddr.bit 2 

4 

6 

(saddr.bit) 

←

 1 

 

 

 

sfr.bit 3 

−

 

8 sfr.bit 

←

 1 

 

 

 

A.bit 2 

4 

−

 

A.bit 

←

 1 

 

 

 

PSW.bit 2 

−

 

6 PSW.bit 

←

 1 

× × ×

SET1 

[HL].bit 2 

6 

8 

(HL).bit 

←

 1 

 

 

 

saddr.bit 2 

4 

6 

(saddr.bit) 

←

 0 

 

 

 

sfr.bit 3 

−

 

8 sfr.bit 

←

 0 

 

 

 

A.bit 2 

4 

−

 

A.bit 

←

 0 

 

 

 

PSW.bit 2 

−

 

6 PSW.bit 

←

 0 

× × ×

CLR1 

[HL].bit 2 

6 

8 

(HL).bit 

←

 0 

 

 

 

SET1 

CY 1 

2 

−

 

CY 

←

 1 

 

 

1

CLR1 

CY 1 

2 

−

 

CY 

←

 0 

 

 

0

Bit 

manipulate 

NOT1 

CY 1 

2 

−

 

CY 

←

 CY 

 

 

×

Notes 1.

  When the internal high-speed RAM area is accessed or for an instruction with no data access 

 

2.

  When an area except the internal high-speed RAM area is accessed 

 

Remarks 1.

 One instruction clock cycle is one cycle of the CPU clock (f

CPU

) selected by the processor clock 

control register (PCC). 

 

2.

  This clock cycle applies to the internal ROM program. 

 

 

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Summary of Contents for mPD78F0730

Page 1: ...1V0UD00 1st edition Date Published December 2007 NS CP K Printed in Japan 2007 PD78F0730 PD78F0730 8 Bit Single Chip Microcontroller Preliminary User s Manual Downloaded from Elcodis com electronic co...

Page 2: ...Preliminary User s Manual U19014EJ1V0UD 2 MEMO Downloaded from Elcodis com electronic components distributor...

Page 3: ...d floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounte...

Page 4: ...ibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and saf...

Page 5: ...set Explanation of each instruction How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To gain...

Page 6: ...elated to Development Tools Software User s Manuals Document Name Document No Operation U17199E Language U17198E RA78K0 Ver 3 80 Assembler Package Structured Assembly Language U17197E Operation U17201...

Page 7: ...tor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website ht...

Page 8: ...6 2 2 11 USBREGC 26 2 2 12 VDD and EVDD 26 2 2 13 VSS and EVSS 26 2 2 14 FLMD0 26 2 3 Pin I O Circuits and Recommended Connection of Unused Pins 27 CHAPTER 3 CPU ARCHITECTURE 30 3 1 Memory Space 30 3...

Page 9: ...TOR 81 5 1 Functions of Clock Generator 81 5 2 Configuration of Clock Generator 82 5 3 Registers Controlling Clock Generator 84 5 4 System Clock Oscillator 94 5 4 1 X1 oscillator 94 5 4 2 Internal hig...

Page 10: ...178 7 2 Configuration of 8 Bit Timer Event Counters 50 and 51 178 7 3 Registers Controlling 8 Bit Timer Event Counters 50 and 51 181 7 4 Operations of 8 Bit Timer Event Counters 50 and 51 186 7 4 1 Op...

Page 11: ...CSI10 270 CHAPTER 12 USB FUNCTION CONTROLLER USBF 271 12 1 Overview 271 12 2 Configuration 272 12 3 Requests 274 12 3 1 Automatic requests 274 12 3 2 Other requests 281 12 4 Register Configuration 28...

Page 12: ...r on Clear Circuit 433 CHAPTER 17 LOW VOLTAGE DETECTOR 435 17 1 Functions of Low Voltage Detector 435 17 2 Configuration of Low Voltage Detector 435 17 3 Registers Controlling Low Voltage Detector 436...

Page 13: ...tion of flag operation column 474 21 2 Operation List 475 21 3 Instructions Listed by Addressing Type 483 CHAPTER 22 ELECTRICAL SPECIFICATIONS TARGET 486 CHAPTER 23 PACKAGE DRAWINGS 502 CHAPTER 24 CAU...

Page 14: ...On chip power on clear POC circuit and low voltage detector LVI On chip watchdog timer operable with the internal low speed oscillation clock I O ports 19 N ch open drain 2 Timer 5 channels 16 bit ti...

Page 15: ...0 P120 INTP0 RESET FLMD0 P122 X2 EXCLK OCD0B P121 X1 OCD0A REGC VDD VSS USBREGC USBP USBM USBPUC 28 27 26 30 29 25 24 23 22 21 20 19 18 16 P10 SCK10 P11 SI10 P12 SO10 P13 TxD6 P14 RxD6 P15 P16 TOH1 P1...

Page 16: ...t 1 P30 to P33 Port 3 P60 P61 Port 6 P120 to P122 Port 12 REGC Regulator capacitance RESET Reset RxD6 Receive data SCK10 Serial clock input output SI10 Serial data input SO10 Serial data output TI000...

Page 17: ...1 TOH1 P16 TI50 TO50 P17 8 bit timer event counter 50 Watchdog timer RxD6 P14 TxD6 P13 Serial interface UART6 TI51 TO51 P33 8 bit timer event counter 51 Serial interface CSI10 SI10 P11 SO10 P12 SCK10...

Page 18: ...inimum instruction execution time 0 125 s internal high speed oscillation clock fRH 16 MHz TYP operation Instruction set 8 bit operation 16 bit operation Multiply divide 8 bits 8 bits 16 bits 8 bits B...

Page 19: ...ter 00 8 Bit Timer Event Counters 50 and 51 8 Bit Timer H1 Watchdog Timer TM00 TM50 TM51 TMH1 Interval timer 1 channel 1 channel 1 channel 1 channel External event counter 1 channel 1 channel 1 channe...

Page 20: ...0 P12 SO10 P13 TxD6 P14 RxD6 P15 P16 TOH1 P17 I O Port 1 8 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input por...

Page 21: ...t clock input to 8 bit timer event counter 50 P17 TO50 TI51 Input External count clock input to 8 bit timer event counter 51 Input port P33 TO51 TO00 Output 16 bit timer event counter 00 output Input...

Page 22: ...e of an on chip pull up resistor can be specified by pull up resistor option register 0 PU0 2 Control mode P00 and P01 function as timer I O a TI000 This is the pin for inputting an external count clo...

Page 23: ...register 1 PU1 2 Control mode P10 to P17 function as serial interface data I O clock I O and timer I O a SI10 This is a serial data input pin of serial interface CSI10 b SO10 This is a serial data ou...

Page 24: ...utput pin from 8 bit timer event counter 51 Cautions 1 In the PD78F0730 be sure to pull the P31 pin down before a reset release to prevent malfunction 2 When writing the flash memory with a flash memo...

Page 25: ...ternal interrupt request input INTP0 for which the valid edge rising edge falling edge or both rising and falling edges can be specified b X1 X2 These are the pins for connecting a resonator for main...

Page 26: ...USB ports 2 2 11 USBREGC This is the pin for connecting regulator output 3 3 V stabilization capacitance for USB ports Connect this pin to VSS via a capacitor 0 47 to 1 0 F recommended 2 2 12 VDD and...

Page 27: ...A I O Connect to EVSS USBPUC 3 C Output Leave open FLMD0 38 Connect to EVSS or VSS Note 4 RESET 2 Input Connect directly to VDD or via a resistor Notes 1 When writing the flash memory with a flash mem...

Page 28: ...h N ch Data OUT VSS Type 5 AG Type 5 AH Pull up enable Data Output disable Input enable EVDD P ch EVDD P ch IN OUT N ch EVSS Pull up enable Data Output disable Input enable EVDD P ch EVDD P ch IN OUT...

Page 29: ...9 Figure 2 1 Pin I O Circuit List 2 2 Type 37 Type 38 Data Output disable Input enable EVDD P ch X1 N ch EVSS RESET Data Output disable Input enable EVDD P ch N ch EVSS RESET P ch N ch X2 Input enable...

Page 30: ...are fixed IMS CFH IXS 0CH Therefore set the value as indicated below 2 To set the memory size set IMS and then IXS Set the memory size so that the internal ROM and internal expansion RAM areas do not...

Page 31: ...F 7 F F H F 9 D 1 H F 9 D 0 H F 0 0 0 H E F F F H 4 0 0 0 H 3 F F F H 0 0 0 0 H 0 8 0 0 H 0 7 F F H 1 0 0 0 H 0 F F F H 0 0 4 0 H 0 0 3 F H 0 0 0 0 H 0 0 8 5 H 0 0 8 4 H 3 F F F H 0 0 8 0 H 0 0 7 F H...

Page 32: ...ock Numbers in Flash Memory Address Value Block Number 0000H to 03FFH 00H 0400H to 07FFH 01H 0800H to 0BFFH 02H 0C00H to 0FFFH 03H 1000H to 13FFH 04H 1400H to 17FFH 05H 1800H to 1BFFH 06H 1C00H to 1FF...

Page 33: ...H to 003FH is reserved as a vector table area The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area Of the 16 bit address the lo...

Page 34: ...when the boot swap is used For details see CHAPTER 18 OPTION BYTE 4 CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2 byte call instruction CALLF 5 On...

Page 35: ...ity Part Number Internal Expansion RAM PD78F0730 2 048 8 bits F000H to F7FFH The internal expansion RAM can also be used as a normal data area similar to the internal high speed RAM as well as a progr...

Page 36: ...or use Figure 3 2 shows correspondence between data memory and addressing For details of each addressing mode see 3 4 Operand Address Addressing Figure 3 2 Correspondence Between Data Memory and Addre...

Page 37: ...C3 PC2 PC1 PC0 0 2 Program status word PSW The program status word is an 8 bit register consisting of various flags set reset by instruction execution Program status word contents are stored in the st...

Page 38: ...egisters PR0L PR0H PR1L PR1H can not be acknowledged Actual request acknowledgement is controlled by the interrupt enable flag IE f Carry flag CY This flag stores overflow and underflow upon add subtr...

Page 39: ...ister pair lower FEE0H SP SP FEE0H FEDFH FEDEH Register pair higher FEDEH b CALL CALLF CALLT instructions when SP FEE0H PC15 to PC8 FEE0H SP SP FEE0H FEDFH FEDEH PC7 to PC0 FEDEH c Interrupt BRK instr...

Page 40: ...P FEDEH Register pair lower FEE0H SP SP FEE0H FEDFH FEDEH Register pair higher FEDEH b RET instruction when SP FEDEH PC15 to PC8 FEE0H SP SP FEE0H FEDFH FEDEH PC7 to PC0 FEDEH c RETI RETB instructions...

Page 41: ...to RP3 Register banks to be used for instruction execution are set by the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching...

Page 42: ...manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved by the assembler for the 16 bit manipulation instruction operand sfrp When specifying an address des...

Page 43: ...W 0000H FF16H 8 bit timer counter 50 TM50 R 00H FF17H 8 bit timer compare register 50 CR50 R W 00H FF18H UF0 EP0 setup register UF0E0ST R 00H FF19H UF0 EP0 write register UF0E0W W Undefined FF1AH 8 bi...

Page 44: ...onous serial interface operation mode register 6 ASIM6 R W 01H FF53H Asynchronous serial interface reception error status register 6 ASIS6 R 00H FF55H Asynchronous serial interface transmission status...

Page 45: ...3 register UF0IF3 R 00H FF96H UF0 interface 4 register UF0IF4 R 00H FF99H Watchdog timer enable register WDTE R W Note 1 1AH 9AH FF9AH UF0 device status register UF0DSTL R W 00H FF9CH UF0 EP0 status...

Page 46: ...0H R W FFH FFE6H Interrupt mask flag register 1L MK1L R W FFH FFE7H Interrupt mask flag register 1H MK1 MK1H R W FFH FFE8H Priority specification flag register 0L PR0L R W FFH FFE9H Priority specifica...

Page 47: ...he value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branche...

Page 48: ...or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the 0800H to 0FFFH area Illustrati...

Page 49: ...ed out when the CALLT addr5 instruction is executed This instruction references the address stored in the memory table from 40H to 7FH and allows branching to the entire memory space Illustration 15 1...

Page 50: ...nction Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Ill...

Page 51: ...by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values that...

Page 52: ...hen an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be desc...

Page 53: ...and address This addressing can be carried out for all of the memory spaces Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting ad...

Page 54: ...ated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 See the Illustration shown...

Page 55: ...FH However the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special fun...

Page 56: ...operand address for addressing the memory This addressing can be carried out for all of the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as...

Page 57: ...dress the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all of the memory spaces...

Page 58: ...sum is used to address the memory Addition is performed by expanding the B or C register contents as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried ou...

Page 59: ...hen the PUSH POP subroutine call and return instructions are executed or the register is saved reset upon generation of an interrupt request With stack addressing only the internal high speed RAM area...

Page 60: ...P121 and P122 VDD P121 and P122 Non port pins The PD78F0730 is provided with the ports shown in Figure 4 1 which enable variety of control operations The functions of each port are shown in Table 4 2...

Page 61: ...in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Analog input TI51 TO51 P60 P61 I O Port 6 2 bit I O port Output of P60 and P61 is N ch open drain output 6 V t...

Page 62: ...ed in 1 bit units by pull up resistor option register 0 PU0 This port can also be used for timer I O Reset signal generation sets port 0 to input mode Figures 4 2 and 4 3 show block diagrams of port 0...

Page 63: ...TO00 WRPU RD WRPORT WRPM PU01 Alternate function Output latch P01 PM01 Alternate function EVDD P ch Selector Internal bus PU0 PM0 P0 P0 Port register 0 PU0 Pull up resistor option register 0 PM0 Port...

Page 64: ...ock I O and timer I O Reset signal generation sets port 1 to input mode Figures 4 4 to 4 9 show block diagrams of port 1 Caution To use P10 SCK10 and P12 SO10 as general purpose ports set serial opera...

Page 65: ...SI10 P14 RxD6 WRPU RD WRPORT WRPM PU11 PU14 Alternate function Output latch P11 P14 PM11 PM14 EVDD P ch Selector Internal bus PU1 PM1 P1 P1 Port register 1 PU1 Pull up resistor option register 1 PM1 P...

Page 66: ...SO10 P16 TOH1 WRPU RD WRPORT WRPM PU12 PU16 Output latch P12 P16 PM12 PM16 Alternate function EVDD P ch Selector Internal bus PU1 PM1 P1 P1 Port register 1 PU1 Pull up resistor option register 1 PM1 P...

Page 67: ...13 P13 TxD6 WRPU RD WRPORT WRPM PU13 Output latch P13 PM13 Alternate function EVDD P ch Internal bus Selector PU1 PM1 P1 P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode registe...

Page 68: ...Diagram of P15 P15 WRPU WRPORT WRPM PU15 PM15 EVDD P ch PU1 PM1 RD P1 Selector Output latch P15 Internal bus P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read...

Page 69: ...TO50 WRPU RD WRPORT WRPM PU17 Alternate function Output latch P17 PM17 Alternate function EVDD P ch Selector Internal bus PU1 PM1 P1 P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port...

Page 70: ...nction 2 When writing the flash memory with a flash memory programmer connect P31 INTP2 OCD1A as follows P31 INTP2 OCD1A Connect to EVSS via a resistor 10 k recommended The above connection is not nec...

Page 71: ...TO51 WRPU RD WRPORT WRPM PU33 Alternate function Output latch P33 PM33 Alternate function EVDD P ch Selector Internal bus PU3 PM3 P3 P3 Port register 3 PU3 Pull up resistor option register 3 PM3 Port...

Page 72: ...put of the P60 and P61 pins is N ch open drain output 6 V withstanding voltage Reset signal generation sets port 6 to input mode Figure 4 12 shows a block diagram of port 6 Figure 4 12 Block Diagram o...

Page 73: ...the main system clock EXCLK the X1 oscillation mode or external clock input mode must be set by using the clock operation mode select register OSCCTL for details see 5 3 1 Clock operation mode select...

Page 74: ...0 INTP0 WRPU RD WRPORT WRPM PU120 Alternate function Output latch P120 PM120 EVDD P ch PU12 PM12 P12 Selector Internal bus P12 Port register 12 PU12 Pull up resistor option register 12 PM12 Port mode...

Page 75: ...PM122 PM12 P12 RD WRPORT WRPM Output latch P121 PM121 PM12 P12 EXCLK OSCSEL OSCCTL OSCSEL OSCSELS OSCCTL P121 X1 OCD0A OSCSEL OSCCTL OSCSEL OSCCTL Internal bus Selector Selector P12 Port register 12...

Page 76: ...l generation sets these registers to FFH When port pins are used as alternate function pins set the port mode register by referencing 4 5 Settings of Port Mode Register and Output Latch When Using Alt...

Page 77: ...signal generation sets these registers to 00H Figure 4 16 Format of Port Register 7 0 Symbol P0 6 0 5 0 4 0 3 0 2 0 1 P01 0 P00 Address FF00H After reset 00H output latch R W R W P17 P1 P16 P15 P14 P1...

Page 78: ...d bits used as alternate function output pins regardless of the settings of PU0 PU1 PU3 and PU12 These registers can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation...

Page 79: ...atus does not change Once data is written to the output latch it is retained until data is written to the output latch again The data of the output latch is cleared when a reset signal is generated 4...

Page 80: ...0 INTP0 Input 1 P121 X1 Note X2 Note P122 EXCLK Note Input Note When using the P121 and P122 pins to connect a resonator for the main system clock X1 X2 or to input an external clock for the main syst...

Page 81: ...can be disabled by executing the STOP instruction or using MOC As the main system clock a high speed system clock X1 clock or external main system clock or internal high speed oscillation clock can b...

Page 82: ...Configuration of Clock Generator The clock generator includes the following hardware Table 5 1 Configuration of Clock Generator Item Configuration Control registers Clock operation mode select regist...

Page 83: ...nal bus Internal bus Main system clock switch Peripheral hardware clock switch Controller Main clock mode register MCM Peripheral hardware clock fPRS CPU clock fCPU Processor clock control register PC...

Page 84: ...L Internal low speed oscillation clock frequency 9 fUSB USB clock oscillation frequency 5 3 Registers Controlling Clock Generator The following ten registers are used to control the clock generator Cl...

Page 85: ...z fXH Cautions 1 Be sure to set AMPH to 1 if the high speed system clock oscillation frequency exceeds 10 MHz 2 Set AMPH before setting the peripheral functions after a reset release The value of AMPH...

Page 86: ...mum instruction execution time is as shown in Table 5 2 Table 5 2 Relationship Between CPU Clock and Minimum Instruction Execution Time Minimum Instruction Execution Time 2 fCPU High Speed System Cloc...

Page 87: ...gh speed oscillator LSRSTOP Internal low speed oscillator oscillating stopped 0 Internal low speed oscillator oscillating 1 Internal low speed oscillator stopped RSTOP Internal high speed oscillator o...

Page 88: ...TOP X1 oscillation mode External clock input mode 0 X1 oscillator operating External clock from EXCLK pin is enabled 1 X1 oscillator stopped External clock from EXCLK pin is disabled Cautions 1 When s...

Page 89: ...ion clock fRH 1 0 Setting prohibited 1 1 High speed system clock fXH High speed system clock fXH MCS Main system clock status 0 Operates with internal high speed oscillation clock 1 Operates with high...

Page 90: ...0 0 2 11 fX min 170 7 s min 128 s min 1 1 0 0 0 2 13 fX min 682 7 s min 512 s min 1 1 1 0 0 2 14 fX min 1 37 ms min 1 024 msmin 1 1 1 1 0 2 15 fX min 2 73 ms min 2 048 ms min 1 1 1 1 1 2 16 fX min 5 4...

Page 91: ...z 0 0 1 2 11 fX 170 7 s 128 s 0 1 0 2 13 fX 682 7 s 512 s 0 1 1 2 14 fX 1 37 ms 1 024 ms 1 0 0 2 15 fX 2 73 ms 2 048 ms 1 0 1 2 16 fX 5 46 ms 4 096 ms Other than above Setting prohibited Cautions 1 To...

Page 92: ...atio for clock supplied to PLL PLL XSEL PLLM Supply clock Multiplication ratio selection 0 0 Setting prohibited Setting prohibited 1 Setting prohibited Setting prohibited 1 0 fXH 2 x8 Note 1 1 fXH 4 x...

Page 93: ...UCKC Address FFA7H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 UCKC UCKCNT 0 0 0 0 0 0 0 UCKCNT USB macro clock supply control 0 Clock supply to USB macro stopped 1 Clock supplied to USB macro Caution...

Page 94: ...the broken lines in the Figure 5 11 to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the...

Page 95: ...nator Connection 2 2 c Wiring near high alternating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates VSS X1 X2 VSS X1 X2 A B C Pmn VDD High current...

Page 96: ...nd the clock of 8 bit timer H1 The internal low speed oscillation clock cannot be used as the CPU clock Can be stopped by software or Cannot be stopped can be selected by the option byte When Can be s...

Page 97: ...clock is set as the CPU clock by the default setting the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released However the start cl...

Page 98: ...system clock 5 When switching the CPU clock to the X1 clock wait for the clock oscillation to stabilize and then set switching via software see 3 in 5 6 1 Example of controlling high speed system clo...

Page 99: ...dure when oscillating the X1 clock 1 Setting frequency OSCCTL register Using AMPH set the gain of the on chip oscillator according to the frequency to be used AMPH Note Operating Frequency Control 0 f...

Page 100: ...uency 2 Setting P121 X1 and P122 X2 EXCLK pins and selecting operation mode OSCCTL register When EXCLK and OSCSEL are set to 1 the mode is switched from port mode to external clock input mode EXCLK OS...

Page 101: ...Clock fCPU Selection 0 0 0 fXP 0 0 1 fXP 2 default 0 1 0 fXP 2 2 0 1 1 fXP 2 3 1 0 0 fXP 2 4 0 Other than above Setting prohibited 4 Example of setting procedure when stopping the high speed system c...

Page 102: ...mples of clock setting procedures for the following cases 1 When restarting oscillation of the internal high speed oscillation clock 2 When using internal high speed oscillation clock as CPU clock and...

Page 103: ...Internal high speed oscillation clock fRH Caution If the internal high speed oscillation clock is selected as the main system clock a clock other than the internal high speed ocsillation clock cannot...

Page 104: ...tion clock The internal low speed oscillation clock cannot be used as the CPU clock Only the following peripheral hardware can operate with this clock Watchdog timer 8 bit timer H1 if fRL fRL 2 7 or f...

Page 105: ...et to 1 in order to select 12 times 3 Setting XSEL to 1 MCM register When XSEL is set to 1 the high speed system clock is supplied to the PLL 4 Clearing PLLSTOP to 0 PLLC register When PLLSTOP is clea...

Page 106: ...l Hardware and Register Setting Supplied Clock Clock Supplied to CPU Clock Supplied to Peripheral Hardware XSEL CSS MCM0 EXCLK Internal high speed oscillation clock 0 0 X1 clock 1 0 1 0 External main...

Page 107: ...rnal high speed oscillator Selectable by CPU X1 oscillation EXCLK input Operating Regulator Operating in normal mode Internal low speed oscillator Operable Internal high speed oscillator Operating X1...

Page 108: ...sters Setting Flag of SFR Register Status Transition AMPH EXCLK OSCSEL MSTOP OSTC Register XSEL MCM0 A B C X1 clock fXH 10 MHz 0 0 1 0 Must be checked 1 1 A B C external main clock fXH 10 MHz 0 1 1 0...

Page 109: ...set Unnecessary if the CPU is operating with the high speed system clock Note The value of this flag can be changed only once after a reset release This setting is not necessary if it has already bee...

Page 110: ...he CPU clock and processing after changing the CPU clock are shown below Table 5 5 Changing CPU Clock CPU Clock Before Change After Change Condition Before Change Processing After Change X1 clock Stab...

Page 111: ...speed system clock The actual switchover operation is not performed immediately after rewriting to MCM0 operation continues on the pre switchover clock for several clocks see Table 5 7 Whether the CPU...

Page 112: ...speed system clock MSTOP 1 5 6 10 Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the PD78F0730 Table 5 9 Peripheral Hardware and Source...

Page 113: ...h any selected frequency 3 External event counter 16 bit timer event counter 00 can measure the number of pulses of an externally input signal 4 One shot pulse output 16 bit timer event counter 00 can...

Page 114: ...register 0 P0 Figure 6 1 shows the block diagram Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 00 Internal bus Capture compare control resister 00 CRC00 fPRS fPRS 22 fPRS TI000 P00 2 PRM001PR...

Page 115: ...edge to the TI000 pin If TM00 and CR000 match in the mode in which the clear start occurs when TM00 and CR000 match OSPT00 is set to 1 or the valid edge is input to the TI000 pin in one shot pulse ou...

Page 116: ...When CR010 is used as a capture register The count value of TM00 is captured to CR010 when a capture trigger is input It is possible to select the valid edge of the TI000 pin as the capture trigger Th...

Page 117: ...ion of edge to be captured 01 Rising 00 Falling TI000 pin input Note 11 Both edges Capture operation of CR010 Interrupt signal INTTM010 signal is generated Note The capture operation of CR010 is not a...

Page 118: ...that sets the 16 bit timer event counter 00 operation mode TM00 clear mode and output timing and detects an overflow Rewriting TMC00 is prohibited during operation when TMC003 and TMC002 other than 0...

Page 119: ...d CR000 TMC001 Condition to reverse timer output TO00 0 Match between TM00 and CR000 or match between TM00 and CR010 1 Match between TM00 and CR000 or match between TM00 and CR010 Trigger input of TI0...

Page 120: ...Captures on valid edge of TI010 pin 1 Captures on valid edge of TI000 pin by reverse phase Note The valid edge of the TI010 and TI000 pin is set by PRM00 If ES001 and ES000 are set to 11 both edges w...

Page 121: ...ten while only OSPT00 is operating when TMC003 and TMC002 other than 00 Rewriting the other bits is prohibited during operation However TOC004 can be rewritten during timer operation as a means to rew...

Page 122: ...even when TOC004 0 LVS00 LVR00 Setting of TO00 pin output status 0 0 No change 0 1 Initial value of TO00 pin output is low level TO00 pin output is cleared to 0 1 0 Initial value of TO00 pin output is...

Page 123: ...10 pin is detected as a rising edge Note this when the TI000 or TI010 pin is pulled up However the rising edge is not detected when the timer operation has been once stopped and then is enabled again...

Page 124: ...pins for timer input set PM00 and PM01 to 1 At this time the output latches of P00 and P01 may be 0 or 1 PM0 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation set...

Page 125: ...INTTM000 is generated This INTTM000 signal enables TM00 to operate as an interval timer Remarks 1 For the setting of I O pins see 6 3 6 Port mode register 0 PM0 2 For how to enable the INTTM000 inter...

Page 126: ...d Prescaler mode register 00 PRM00 0 0 0 0 0 3 2 PRM001 PRM000 ES101 ES100 ES001 ES000 Selects count clock 0 0 1 0 1 e 16 bit timer counter 00 TM00 By reading TM00 the count value can be read f 16 bi...

Page 127: ...002 bits 11 TMC003 TMC002 bits 00 Register initial setting PRM00 register CRC00 register CR000 register port setting Initial setting of these registers is performed before setting the TMC003 and TMC00...

Page 128: ...ted and output of the TO00 pin is inverted This TO00 pin output that is inverted at fixed intervals enables TO00 to output a square wave Remarks 1 For the setting of I O pins see 6 3 6 Port mode regis...

Page 129: ...match between TM00 and CR000 0 1 1 d Prescaler mode register 00 PRM00 0 0 0 0 0 3 2 PRM001 PRM000 ES101 ES100 ES001 ES000 Selects count clock 0 0 1 0 1 e 16 bit timer counter 00 TM00 By reading TM00 t...

Page 130: ...initial setting PRM00 register CRC00 register TOC00 registerNote CR000 register port setting Initial setting of these registers is performed before setting the TMC003 and TMC002 bits to 11 Starts cou...

Page 131: ...r later Number of times of detection of valid edge of external event Set value of CR000 1 However the first match interrupt immediately after the timer event counter has started operating is generated...

Page 132: ...S100 ES001 ES000 Selects count clock specifies valid edge of TI000 00 Falling edge detection 01 Rising edge detection 10 Setting prohibited 11 Both edges detection 0 1 1 e 16 bit timer counter 00 TM00...

Page 133: ...2 TMC003 TMC002 bits 11 TMC003 TMC002 bits 00 Register initial setting PRM00 register CRC00 register CR000 register port setting Initial setting of these registers is performed before setting the TMC...

Page 134: ...e count value of TM00 is captured to CR000 and the INTTM000 signal is generated when the valid edge is input to the TI010 pin or when the phase reverse to that of the valid edge is input to the TI000...

Page 135: ...M 00 N b TOC00 13H PRM00 10H CRC00 00H TMC00 0AH TM00 register 0000H Operable bits TMC003 TMC002 Count clear input TI000 pin input Compare register CR000 Compare match interrupt INTTM000 Compare regi...

Page 136: ...TI000 Pin Valid Edge Input CR000 Compare Register CR010 Capture Register 1 2 a TOC00 13H PRM00 10H CRC00 04H TMC00 08H CR000 0001H TM00 register 0000H Operable bits TMC003 TMC002 Capture count clear...

Page 137: ...pin output 0003H 0003H 10 Q P N M S 00 0000H M 4 4 4 4 N S P Q This is an application example where the width set to CR000 4 clocks in this example is to be output from the TO00 pin when the count va...

Page 138: ...Diagram of Clear Start Mode Entered by TI000 Pin Valid Edge Input CR000 Capture Register CR010 Compare Register Timer counter TM00 Clear Output controller Edge detection Capture register CR000 Captur...

Page 139: ...S P This is an application example where the output level of the TO00 pin is to be inverted when the count value has been captured cleared TM00 is cleared at the rising edge detection of the TI000 pin...

Page 140: ...the TO00 pin when the count value has been captured cleared TM00 is cleared to 0000H at the rising edge detection of the TI000 pin and captured to CR000 at the falling edge detection of the TI000 pin...

Page 141: ...tecting the valid edge of the TI010 pin is used Figure 6 29 Timing Example of Clear Start Mode Entered by TI000 Pin Valid Edge Input CR000 Capture Register CR010 Capture Register 1 3 a TOC00 13H PRM00...

Page 142: ...003 TMC002 Capture trigger input TI010 pin input Capture register CR000 Capture interrupt INTTM000 Capture count clear input TI000 Capture register CR010 Capture interrupt INTTM010 10 R S T O L M N P...

Page 143: ...reverse to the falling edge of the TI000 pin i e rising edge and to CR010 at the falling edge of the TI000 pin The high and low level widths of the input pulse can be calculated by the following expr...

Page 144: ...pture register 0 CR010 used as compare register 1 CR010 used as capture register 0 TI010 pin is used as capture trigger of CR000 1 Reverse phase of TI000 pin is used as capture trigger of CR000 c 16 b...

Page 145: ...re register and when its value matches the count value of TM00 an interrupt signal INTTM000 is generated The count value of TM00 is not cleared To use this register as a capture register select either...

Page 146: ...g PRM00 register CRC00 register TOC00 registerNote CR000 CR010 registers TMC00 TMC001 bit port setting Initial setting of these registers is performed before setting the TMC003 and TMC002 bits to 10 S...

Page 147: ...h CR000 and CR010 are used as compare registers One of CR000 or CR010 is used as a compare register and the other is used as a capture register Both CR000 and CR010 are used as capture registers Remar...

Page 148: ...are registers are used in the free running timer mode The output level of the TO00 pin is reversed each time the count value of TM00 matches the set value of CR000 or CR010 When the count value matche...

Page 149: ...ow flag OVF00 01 M N S P Q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000H 0001H M N S P Q This is an application example where a compare register and a capture register are used at t...

Page 150: ...l Interrupt signal INTTM010 Interrupt signal INTTM000 Capture register CR010 Operable bits TMC003 TMC002 Count clock Edge detection TI000 pin Edge detection TI010 pin Selector Remark If both CR000 and...

Page 151: ...gister CR000 Capture interrupt INTTM000 Overflow flag OVF00 01 M A B C D E N S P Q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000H A B C D E 0000H M N S P Q This is an application exa...

Page 152: ...ure interrupt INTTM000 Capture trigger input TI000 Capture register CR010 Capture interrupt INTTM010 01 L M P S N O R Q T 00 0000H 0000H L M N O P Q R S T L L This is an application example where both...

Page 153: ...egister 1 CR000 used as capture register 0 CR010 used as compare register 1 CR010 used as capture register 0 TI010 pin is used as capture trigger of CR000 1 Reverse phase of TI000 pin is used as captu...

Page 154: ...When this register is used as a compare register and when its value matches the count value of TM00 an interrupt signal INTTM000 is generated The count value of TM00 is not cleared To use this registe...

Page 155: ...C002 bits 0 1 Register initial setting PRM00 register CRC00 register TOC00 registerNote CR000 CR010 register TMC00 TMC001 bit port setting Initial setting of these registers is performed before settin...

Page 156: ...ws Pulse cycle Set value of CR000 1 Count clock cycle Duty Set value of CR010 1 Set value of CR000 1 Caution To change the duty factor value of CR010 during operation see 6 5 1 Rewriting CR010 during...

Page 157: ...0 00 Disables one shot pulse output Specifies initial value of TO00 output F F 0 1 1 1 d Prescaler mode register 00 PRM00 0 0 0 0 0 3 2 PRM001 PRM000 ES101 ES100 ES001 ES000 Selects count clock 0 0 1...

Page 158: ...tting PRM00 register CRC00 register TOC00 registerNote CR000 CR010 registers port setting Initial setting of these registers is performed before setting the TMC003 and TMC002 bits Starts count operati...

Page 159: ...detecting the valid edge of the TI000 pin while the one shot pulse is output To output the one shot pulse again generate the trigger after the current one shot pulse output has completed 2 To use onl...

Page 160: ...R000 used as compare register CR010 used as compare register c 16 bit timer output control register 00 TOC00 0 0 1 1 1 0 1 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 Enables TO00 pin output Inverts...

Page 161: ...shot pulse is output When the value of TM00 matches that of CR000 an interrupt signal INTTM000 is generated and the output level of the TO00 pin is inverted g 16 bit capture compare register 010 CR010...

Page 162: ...g OVF00 Compare register CR000 Compare match interrupt INTTM000 Compare register CR010 Compare match interrupt INTTM010 TO00 pin output TO00 output control bits TOE00 TOC004 TOC001 N M N M N M 01 or 1...

Page 163: ...e setting the TMC003 and TMC002 bits Starts count operation START 1 Count operation start flow 2 One shot trigger input flow TMC003 TMC002 bits 00 The counter is initialized and counting is stopped by...

Page 164: ...bits TMC003 TMC002 Count clock Edge detection TI000 pin Edge detection TI010 pin Selector Figure 6 47 Block Diagram of Pulse Width Measurement Clear Start Mode Entered by TI000 Pin Valid Edge Input Ti...

Page 165: ...egister in advance If an overflow occurs the value becomes negative if the previously captured value is simply subtracted from the current captured value and therefore a borrow occurs bit 0 CY of the...

Page 166: ...idth low level width and cycle are calculated If an overflow occurs the value becomes negative if one captured value is simply subtracted from another and therefore a borrow occurs bit 0 CY of the pro...

Page 167: ...e value stored in CR010 as a cycle Clear bit 0 OVF00 of 16 bit timer mode control register 00 TMC00 to 0 Figure 6 50 Timing Example of Pulse Width Measurement 3 TMC00 08H PRM00 10H CRC00 07H FFFFH TM0...

Page 168: ...r 0 TI010 pin is used as capture trigger of CR000 1 Reverse phase of TI000 pin is used as capture trigger of CR000 c 16 bit timer output control register 00 TOC00 0 0 0 0 0 LVR00 LVS00 TOC004 OSPE00 O...

Page 169: ...r is used as a capture register Either the TI000 or TI010 pin is selected as a capture trigger When a specified edge of the capture trigger is detected the count value of TM00 is stored in CR000 g 16...

Page 170: ...egister CR000 Capture interrupt INTTM000 01 D00 D00 D01 D01 D02 D02 D03 D03 D04 D04 D10 D10 D11 D11 D12 D12 D13 D13 00 00 0000H 0000H 1 2 2 2 2 2 2 2 2 2 3 b Example of clear start mode entered by TI0...

Page 171: ...ter initial setting PRM00 register CRC00 register port setting Initial setting of these registers is performed before setting the TMC003 and TMC002 bits Starts count operation START 1 Count operation...

Page 172: ...MK010 1 2 Disable reversal of the timer output when the value of TM00 matches that of CR010 TOC004 0 3 Change the value of CR010 4 Wait for one cycle of the count clock of TM00 5 Enable reversal of th...

Page 173: ...00 LVS00 bit TOC00 LVR00 bit Operable bits TMC003 TMC002 TO00 pin output INTTM000 signal 1 00 2 1 3 4 4 4 01 10 or 11 1 The TO00 pin output goes high when LVS00 and LVR00 10 2 The TO00 pin output goes...

Page 174: ...ed TOC00 00H As free running timer As PPG output Setting identical values or 0000H to CR000 and CP010 is prohibited As one shot pulse output As pulse width measurement TOC00 00H 2 Timer start errors A...

Page 175: ...d the value of CR000 CR010 after INTTM000 INTTM010 is generated Figure 6 56 Timing of Holding Data by Capture Register N N 1 N 2 X N 1 M M 1 M 2 Count pulse TM00 count value Edge input INTTM010 Value...

Page 176: ...Flag FFFEH FFFFH FFFFH 0000H 0001H Count pulse TM00 INTTM000 OVF00 CR000 b Clearing OVF00 flag Even if the OVF00 flag is cleared to 0 after TM00 overflows and before the next count clock is counted b...

Page 177: ...e INTTM000 signal is generated as an external interrupt signal Mask the INTTM000 signal when the external interrupt is not used 10 Edge detection a Specifying valid edge after reset If the operation o...

Page 178: ...clude the following hardware Table 7 1 Configuration of 8 Bit Timer Event Counters 50 and 51 Item Configuration Timer register 8 bit timer counter 5n TM5n Register 8 bit timer compare register 5n CR5n...

Page 179: ...s Invert level 8 bit timer mode control register 50 TMC50 Note 1 Note 2 Output latch P17 Figure 7 2 Block Diagram of 8 Bit Timer Event Counter 51 TI51 TO51 P33 fPRS 24 fPRS 26 fPRS 28 fPRS 212 fPRS fP...

Page 180: ...en by an 8 bit memory manipulation instruction Except in PWM mode the value set in CR5n is constantly compared with the 8 bit timer counter 5n TM5n count value and an interrupt request INTTM5n is gene...

Page 181: ...a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets TCL5n to 00H Remark n 0 1 Figure 7 5 Format of Timer Clock Selection Register 50 TCL50 Address FF6AH After reset 00H R W S...

Page 182: ...fPRS 12 MHz fPRS 16 MHz 0 0 0 TI51 pin falling edge 0 0 1 TI51 pin rising edge 0 1 0 fPRS 12 MHz 16 MHz 0 1 1 fPRS 2 6 MHz 8 MHz 1 0 0 fPRS 2 4 750 kHz 1 MHz 1 0 1 fPRS 2 6 187 5 kHz 250 kHz 1 1 0 fP...

Page 183: ...50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50 TCE50 TM50 count operation control 0 After clearing to 0 count operation disabled counter stopped 1 Count operation start TMC506 TM50 operating mode selection 0...

Page 184: ...C511 Timer F F control Active level selection 0 Inversion operation disabled Active high 1 Inversion operation enabled Active low TOE51 Timer output control 0 Output disabled TM51 output is low level...

Page 185: ...1 and PM3 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets these registers to FFH Figure 7 9 Format of Port Mode Register 1 PM1 Address FF21H After reset FFH...

Page 186: ...e count clock CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on a match of TM5n and CR5n TMC5n 0000 0B Don t care 2 After TCE5n 1 is set the count operat...

Page 187: ...Timing 2 2 b When CR5n 00H t Interval time Count clock TM5n CR5n TCE5n INTTM5n 00H 00H 00H 00H 00H c When CR5n FFH t Count clock TM5n CR5n TCE5n INTTM5n 01H FEH FFH 00H FEH FFH 00H FFH FFH FFH Interva...

Page 188: ...edge TI5n pin falling edge TCL5n 00H TI5n pin rising edge TCL5n 01H CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on match of TM5n and CR5n disable the...

Page 189: ...ich clear start occurs on a match of TM5n and CR5n LVS5n LVR5n Timer Output F F Status Setting 1 0 Timer output F F clear 0 default output value of TO5n pin low level 0 1 Timer output F F set 1 defaul...

Page 190: ...bit 6 TMC5n6 of 8 bit timer mode control register 5n TMC5n is set to 1 The duty pulse determined by the value set to 8 bit timer compare register 5n CR5n is output from TO5n Set the active level widt...

Page 191: ...counter 50 P17 PM17 8 bit timer event counter 51 P33 PM33 PWM output operation 1 PWM output output from TO5n outputs an inactive level until an overflow occurs 2 When an overflow occurs the active le...

Page 192: ...e level t 2 Active level b CR5n 00H Count clock TM5n CR5n TCE5n INTTM5n 01H 00H FFH 00H 01H 02H 00H FFH 00H 01H 02H M 00H TO5n L Inactive level t c CR5n FFH TM5n CR5n TCE5n INTTM5n TO5n 01H 00H FFH 00...

Page 193: ...n 1 CR5n change N M N N 1 N 2 FFH 00H 01H M M 1 M 2 FFH 00H 01H 02H M M 1 M 2 N 02H M H 2 t b CR5n value is changed from N to M after clock rising edge of FFH Value is transferred to CR5n at second ov...

Page 194: ...one clock may occur in the time required for a match signal to be generated after timer start This is because 8 bit timer counters 50 and 51 TM50 TM51 are started asynchronously to the count clock Fi...

Page 195: ...g hardware Table 8 1 Configuration of 8 Bit Timer H1 Item Configuration Timer register 8 bit timer counter H1 Registers 8 bit timer H compare register 01 CMP01 8 bit timer H compare register 11 CMP11...

Page 196: ...ister 1 TMCYC1 INTTMH1 INTTM51 Selector fPRS fPRS 22 fPRS 24 fPRS 26 fPRS 212 fRL fRL 27 fRL 29 Interrupt generator Output controller Level inversion PM16 Output latch P16 1 0 F F R PWM mode signal Ca...

Page 197: ...bit timer counter H1 and when the two values match inverts the output level of TOH1 No interrupt request signal is generated In the carrier generator mode the CMP11 register always compares the value...

Page 198: ...mode register 1 TMHMD1 8 bit timer H carrier control register 1 TMCYC1 Port mode register 1 PM1 Port register 1 P1 1 8 bit timer H mode register 1 TMHMD1 This register controls the mode of timer H Th...

Page 199: ...fRL 27 fRL 29 fRL CKS12 0 0 0 0 1 1 1 1 CKS11 0 0 1 1 0 0 1 1 CKS10 0 1 0 1 0 1 0 1 fPRS 12 MHz 12 MHz 3 MHz 750 kHz 187 5 kHz 2 93 kHz 1 88 kHz TYP 0 47 kHz TYP 240 kHz TYP Count clock selection fPRS...

Page 200: ...rier output disabled status low level status Carrier output enabled status RMC1 1 Carrier pulse output RMC1 0 High level status NRZ1 0 1 Carrier pulse output status flag 0 1 2 3 4 5 6 7 Note Bit 0 is...

Page 201: ...ve Output Operation i Setting timer H mode register 1 TMHMD1 0 0 1 0 1 0 1 0 0 0 1 0 1 TMMD10 TOLEV1 TOEN1 CKS11 CKS12 TMHE1 TMHMD1 CKS10 TMMD11 Timer output setting Default setting of timer output le...

Page 202: ...n is enabled by setting the TMHE1 bit to 1 The count clock starts counting no more than 1 clock after the operation is enabled 2 When the value of 8 bit timer counter H1 matches the value of the CMP01...

Page 203: ...peration when CMP01 FFH 00H Count clock Count start 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 01H FEH Clear Clear FFH 00H FEH FFH 00H FFH Interval time c Operation when CMP01 00H Count clock Cou...

Page 204: ...S12 TMHE1 TMHMD1 CKS10 TMMD11 Timer output enabled Default setting of timer output level PWM output mode selection Count clock fCNT selection Count operation stopped ii Setting CMP01 register Compare...

Page 205: ...perating clocks signal selected by the CKS12 to CKS10 bits of the TMHMD1 register from when the value of the CMP11 register is changed until the value is transferred to the register 2 Be sure to set t...

Page 206: ...ount up At this time TOH1 output remains the default 2 When the values of 8 bit timer counter H1 and the CMP01 register match the TOH1 output level is inverted the value of 8 bit timer counter H1 is c...

Page 207: ...nt clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMP11 FFH 00H c Operation when CMP01 FFH CMP11 FEH Count clock 8 bit timer counter H1...

Page 208: ...Figure 8 10 Operation Timing in PWM Output Mode 3 4 d Operation when CMP01 01H CMP11 00H Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 01H 00H 01H 00H 01H 00H 00H 01H 00H 01H CM...

Page 209: ...H1 output level is inverted and the INTTMH1 signal is output 4 If the CMP11 register value is changed the value is latched and not transferred to the register When the values of 8 bit timer counter H1...

Page 210: ...1 Carrier generation In carrier generator mode 8 bit timer H compare register 01 CMP01 generates a low level width carrier pulse waveform and 8 bit timer H compare register 11 CMP11 generates a high...

Page 211: ...h the count clock of the 8 bit timer H1 and is output as the INTTM5H1 signal 2 The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal...

Page 212: ...the CMP01 register value match the INTTMH1 signal is generated 8 bit timer counter H1 is cleared At the same time the compare register to be compared with 8 bit timer counter H1 is switched from the...

Page 213: ...ven if setting the same value to the CMP11 register 2 Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51 3 Set the values of the CMP01 and CMP11...

Page 214: ...erated the carrier clock signal is inverted and the compare register to be compared with 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register 8 bit timer counter H1 is clea...

Page 215: ...gister to be compared with 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register 8 bit timer counter H1 is cleared to 00H 4 When the count value of 8 bit timer counter H1 ma...

Page 216: ...operating The new value L to which the value of the register is to be changed is latched When the count value of 8 bit timer counter H1 matches the value M of the CMP11 register before the change the...

Page 217: ...able register WDTE If data other than ACH is written to WDTE If data is written to WDTE during a window close period If the instruction is fetched from an area not set by the IMS and IXS registers det...

Page 218: ...5 WINDOW1 WINDOW0 Controlling counter operation of watchdog timer Bit 4 WDTON Overflow time of watchdog timer Bits 3 to 1 WDCS2 to WDCS0 Remark For the option byte see CHAPTER 18 OPTION BYTE Figure 9...

Page 219: ...on byte 0080H To operate watchdog timer set WDTON to 1 WDTON Setting Value WDTE Reset Value 0 watchdog timer count operation disabled 1AH 1 watchdog timer count operation enabled 9AH Cautions 1 If a v...

Page 220: ...starts counting again 4 After that write WDTE the second time or later after a reset release during the window open period If WDTE is written during a window close period an internal reset signal is g...

Page 221: ...rrupt acknowledge time is delayed Set the overflow time and window size taking this delay into consideration 9 4 2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer b...

Page 222: ...he overflow time the watchdog timer is cleared and starts counting again Window open period 100 Counting starts Overflow time Counting starts again when ACH is written to WDTE The window open period t...

Page 223: ...erial interface UART6 is stopped e g in the STOP mode each register stops operating and holds the value immediately before clock supply was stopped The TXD6 pin also holds the value immediately before...

Page 224: ...ceive shift register 6 RXS6 Transmit buffer register 6 TXB6 Transmit shift register 6 TXS6 Control registers Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface...

Page 225: ...Internal bus Baud rate generator Baud rate generator Reception unit Transmission unit Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface operation mod...

Page 226: ...arted when data is written to TXB6 This register can be read or written by an 8 bit memory manipulation instruction Reset signal generation sets this register to FFH Cautions 1 Do not write data to TX...

Page 227: ...of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Figure 10 2 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 1 2 Address FF50H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 AS...

Page 228: ...t does not occur Cautions 1 To start the transmission set POWER6 to 1 and then set TXE6 to 1 To stop the transmission clear TXE6 to 0 and then clear POWER6 to 0 2 To start the reception set POWER6 to...

Page 229: ...E6 0 or if ASIS6 register is read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 0 and RXE6 0 or if ASIS...

Page 230: ...s transferred to transmit shift register 6 TXS6 1 If data is written to transmit buffer register 6 TXB6 if data exists in TXB6 TXSF6 Transmit shift register data flag 0 If POWER6 0 or TXE6 0 or if the...

Page 231: ...kHz 1 MHz 0 1 0 1 fPRS 2 5 375 kHz 500 kHz 0 1 1 0 fPRS 2 6 187 5 kHz 250 kHz 0 1 1 1 fPRS 2 7 93 75 kHz 125 kHz 1 0 0 0 fPRS 2 8 46 875 kHz 62 5 kHz 1 0 0 1 fPRS 2 9 23 438 kHz 31 25 kHz 1 0 1 0 fPR...

Page 232: ...Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8 bit counter 0 0 0 0 0 0 Setting prohibited 0...

Page 233: ...terface data input set PM14 to 1 The output latch of P14 at this time may be 0 or 1 PM1 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets this register to FFH...

Page 234: ...R6 Enables disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit Note 2...

Page 235: ...SRM6 SL6 CL6 PS60 PS61 of the ASIM6 register see Figure 10 2 4 Set bit 7 POWER6 of the ASIM6 register to 1 5 Set bit 6 TXE6 of the ASIM6 register to 1 Transmission is enabled Set bit 5 RXE6 of the ASI...

Page 236: ...l UART Transmit Receive Data Start bit Parity bit D0 D1 D2 D3 D4 1 data frame Character bits D5 D6 D7 Stop bit One data frame consists of the following bits Start bit 1 bit Character bits 7 or 8 bits...

Page 237: ...mmunication data 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2 Data length 7 bits LSB first Parity Odd parity Stop bit 2 bits Communication data 36H 1 data frame Start D0 D1 D2 D3 D4 D5...

Page 238: ...ity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If...

Page 239: ...at the transmit data is sequentially output from TXS6 to the TXD6 pin When transmission is completed the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request...

Page 240: ...F6 flags for judgment Read only the TXBF6 flag when executing continuous transmission TXBF6 Writing to TXB6 Register 0 Writing enabled 1 Writing disabled Caution To transmit data continuously write th...

Page 241: ...umber of times Yes Read ASIF6 TXBF6 0 No No Yes Transmission completion interrupt occurs Read ASIF6 TXSF6 0 No No No Yes Yes Yes Yes Completion of transmission processing Transfer executed necessary n...

Page 242: ...ata 1 Data 3 FF FF Parity Stop Data 2 Parity Stop TXB6 TXS6 TXBF6 TXSF6 Start Start Note Note When ASIF6 is read there is a period in which TXBF6 and TXSF6 1 1 Therefore judge whether writing is enabl...

Page 243: ...or TXE6 Start Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous serial interface transmission status regist...

Page 244: ...reception completion interrupt INTSR6 is generated and the data of RXS6 is written to receive buffer register 6 RXB6 If an overrun error OVE6 occurs however the receive data is not written to RXB6 Ev...

Page 245: ...The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overrun error Reception of the next data is completed before data is read fro...

Page 246: ...output of the match detector changes and the data is sampled as input data Because the circuit is configured as shown in Figure 10 16 the internal processing of the reception operation is delayed by t...

Page 247: ...unter This counter stops operation cleared to 0 when bit 7 POWER6 or bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when POWER6 1 and TXE6 1 The co...

Page 248: ...lock selection register 6 CKSR6 and baud rate generator control register 6 BRGC6 The clock to be input to the 8 bit counter can be set by bits 3 to 0 TPS63 to TPS60 of CKSR6 and the division value fXC...

Page 249: ...s 1 Keep the baud rate error during transmission to within the permissible error range at the reception destination 2 Make sure that the baud rate error during reception satisfies the range shown in 4...

Page 250: ...5 38 0 16 19200 3H 39 19230 8 0 16 5H 13 19230 8 0 16 24000 1H 125 24000 0 00 1H 167 23952 1 0 20 31250 5H 6 31250 0 00 5H 8 31250 0 00 38400 2H 39 38461 5 0 16 4H 13 38461 5 0 16 48000 0H 125 48000 0...

Page 251: ...y bit Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit...

Page 252: ...T6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 10 6 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximu...

Page 253: ...Start bit of second byte Start bit Bit 0 Where the 1 bit data length is FL the stop bit length is FLstp and base clock frequency is fXCLK6 the following expression is satisfied FLstp FL 2 fXCLK6 Ther...

Page 254: ...mode is used to communicate 8 bit data using three lines a serial clock line SCK10 and two serial data lines SI10 and SO10 The processing time of data communication can be shortened in the 3 wire seri...

Page 255: ...10 CSIM10 Serial clock selection register 10 CSIC10 Port mode register 0 PM0 or port mode register 1 PM1 Port register 0 P0 or port register 1 P1 Figure 11 1 Block Diagram of Serial Interface CSI10 In...

Page 256: ...instruction Reset signal generation sets this register to 00H Caution Do not access SOTB10 when CSOT10 1 during serial communication 2 Serial I O shift register 10 SIO10 This is an 8 bit register tha...

Page 257: ...rol in 3 wire serial I O mode 0 Disables operation Note 2 and asynchronously resets the internal circuit Note 3 1 Enables operation TRMD10 Note 4 Transmit receive mode control 0 Note 5 Receive mode tr...

Page 258: ...6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 3 1 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 4 CSI10 serial clock selection CK...

Page 259: ...P10 SCK10 as the clock input pin of the serial interface and P11 SI10 as the data input pin set PM10 and PM11 to 1 At this time the output latches of P10 and P11 may be 0 or 1 PM1 can be set by a 1 bi...

Page 260: ...CSIM10 To set the operation stop mode clear bit 7 CSIE10 of CSIM10 to 0 a Serial operation mode register 10 CSIM10 CSIM10 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal ge...

Page 261: ...ister 1 PM1 Port register 1 P1 The basic procedure of setting an operation in the 3 wire serial I O mode is as follows 1 Set the CSIC10 register see Figure 11 3 2 Set bits 0 4 and 6 CSOT10 DIR10 and T...

Page 262: ...1 1 1 0 0 1 Slave transmission reception Note 3 SI10 SO10 SCK10 input Note 3 1 0 1 Note 1 Note 1 0 1 Master reception SI10 P12 SCK10 output 1 1 Note 1 Note 1 0 0 0 1 Master transmission P11 SO10 SCK10...

Page 263: ...n is started when data is read from serial I O shift register 10 SIO10 After communication has been started bit 0 CSOT10 of CSIM10 is set to 1 When communication of 8 bit data has been completed a com...

Page 264: ...al I O Mode 2 2 b Transmission reception timing Type 2 TRMD10 1 DIR10 0 CKP10 0 DAP10 1 ABH 56H ADH 5AH B5H 6AH D5H SCK10 SOTB10 SIO10 CSOT10 CSIIF10 SO10 SI10 input AAH AAH 55H communication data 55H...

Page 265: ...CKP10 0 DAP10 1 DIR10 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 Writing to SOTB10 or reading from SIO10 SI10 capture CSIIF10 CSOT10 c Type 3 CKP10 1 DAP10 0 DIR10 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 Writ...

Page 266: ...t latch SO10 Writing to SOTB10 or reading from SIO10 First bit 2nd bit The first bit is directly latched by the SOTB10 register to the output latch at the falling or rising edge of SCK10 and output fr...

Page 267: ...ster at the falling edge of the write signal of the SOTB10 register or the read signal of the SIO10 register and output from the SO10 pin via an output selector Then the value of the SOTB10 register i...

Page 268: ...the last bit Figure 11 8 Output Value of SO10 Pin Last Bit 1 2 a Type 1 CKP10 0 DAP10 0 SCK10 SOTB10 SIO10 SO10 Writing to SOTB10 or reading from SIO10 Next request is issued Last bit Output latch b T...

Page 269: ...Type 2 CKP10 0 DAP10 1 SCK10 SOTB10 SIO10 SO10 Last bit Writing to SOTB10 or reading from SIO10 Next request is issued Output latch d Type 4 CKP10 1 DAP10 1 Last bit Next request is issued SCK10 SOTB...

Page 270: ...latch low level output DIR10 0 Value of bit 7 of SOTB10 TRMD10 1 DAP10 1 DIR10 1 Value of bit 0 of SOTB10 Notes 1 The actual output of the SO10 P12 pin is determined according to PM12 and P12 as well...

Page 271: ...Name FIFO Size Bytes Transfer Type Remark Endpoint0 Read 64 Control transfer Endpoint0 Write 64 Control transfer Endpoint1 64 2 Bulk 1 transfer IN 2 buffer configuration Endpoint2 64 2 Bulk 1 transfe...

Page 272: ...r UF0IS2 UF0 INT status 3 register UF0IS3 UF0 INT status 4 register UF0IS4 UF0 INT mask 0 register UF0IM0 UF0 INT mask 1 register UF0IM1 UF0 INT mask 2 register UF0IM2 UF0 INT mask 3 register UF0IM3 U...

Page 273: ...F0 address register UF0ADRS UF0 configuration register UF0CNF UF0 interface 0 register UF0IF0 UF0 interface 1 to 4 registers UF0IF1 to UF0IF4 UF0 descriptor length register UF0DSCL UF0 devise descript...

Page 274: ...e following tables show the request formats and correspondence between requests and decoded values Table 12 2 Request Format Offset Field Name 0 bmRequestType 1 bRequest 2 Lower side 3 wValue Higher s...

Page 275: ...EAR_FEATURE Endpoint 0Note 2 02H 01H 00H 00H 00H 00H 80H 00H 00H ACK NAK ACK NAK ACK NAK CLEAR_FEATURE Endpoint XNote 2 02H 01H 00H 00H 00H H 00H 00H STALL STALL ACK NAK SET_FEATURE DeviceNote 3 00H 0...

Page 276: ...d in the SETUP stage is of less than 8 bytes 2 An ACK response is made even when the host transmits data other than a Null packet in the status stage 3 If the wLength value is 00H during control trans...

Page 277: ...TALL response is made in the status stage Configured state The correct response is made when the CLEAR_FEATURE request has been received only if the target is a device or a request for an endpoint tha...

Page 278: ...GET_DESCRIPTOR request has been received A descriptor of up to 256 bytes can be stored in the UF0CIEm register To return a descriptor of more than 256 bytes set the CDCGDST bit of the UF0MODC registe...

Page 279: ...TALL response is made in the status stage if either of wIndex or wLength is other than the values shown in Table 12 3 A STALL response is also made if the specified device address is greater than 127...

Page 280: ...nterrupt is issued All Halt Features are cleared after the SET_CONFIGURATION request has been completed even if the specified configuration value is the same as the current configuration value If the...

Page 281: ...always initialized again to DATA0 When the currently selected Alternative Setting is to be changed by correctly processing the SET_INTERFACE request the FIFO of the endpoint that is affected is compl...

Page 282: ...AK 0 Do not transmit NAK default value Set this bit to 1 by FW when data should not be received from the USB bus for some reason even when USBF is ready for receiving data In this case USBF continues...

Page 283: ...n before completion of control transfer In this case clear the PROT bit of the UF0IS1 register to 0 by clearing the PROTC bit of the UF0IC1 register to 0 and then read data from the UF0E0ST register a...

Page 284: ...cally executed request is to be changed It postpones reflecting a write access on this bit from FW while an access from SIE is being made Before rewriting the request data register from FW confirm tha...

Page 285: ...sure to clear bits 7 to 3 and 1 If these bits are set to 1 the operation is not guaranteed 1 2 0 UF0EN 0 5 0 0 3 0 2 BKO1NK 1 0 BKI1NK Address FF62H After reset 00H 0 4 6 7 Bit position Bit name Funct...

Page 286: ...atisfied Data is correctly written to the FIFO connected to the CPU bus side writing has been completed and the FIFO is full or the UF0DEND register is set The value of the FIFO counter connected to t...

Page 287: ...in 8 bit units Be sure to clear bits 7 to 3 1 and 0 If these bits are set to 1 the operation is not guaranteed 0 UF0ENM 0 5 0 0 3 0 2 BKO1NKM 1 0 0 Address FF63H After reset 00H 0 4 6 7 Bit position...

Page 288: ...default value This bit is cleared to 0 and the handshake response to the bus is other than STALL when the next SETUP token is received To set the SNDSTL bit to 1 by FW do not write data to the UF0E0W...

Page 289: ...int is not supported by the setting of the UF0EnIM register n 1 2 and the current setting of the interface 0 UF0CLR 0 5 0 0 3 CLREP2 2 CLREP1 1 CLREP0 CLRDEV Address FF65H After reset 00H 0 4 6 7 Bit...

Page 290: ...2 SETEP 1 0 SETDEV Address FF66H After reset 00H 0 4 6 7 Bit position Bit name Function 7 SETCON This bit indicates that a SET_CONFIGURATION request is received and automatically processed 1 Automati...

Page 291: ...in the register 0 No data is in the register default value 2 BKIN1 This bit indicates that data is in the UF0BI1 register FIFO connected to the CPU side By setting the BKI1DED bit of the UF0DEND regi...

Page 292: ...status This bit is meaningful only when an interrupt request is generated 1 Suspend status 0 Resume status default value Because sampling is internally performed with the clock the operation is guaran...

Page 293: ...and therefore the HALT0 bit is also cleared to 0 If Endpoint0 is stalled by the SET_FEATURE Endpoint0 request this bit is not cleared to 0 until the CLEAR_FEATURE Endpoint0 request is received or Halt...

Page 294: ...end status has not occurred default value 2 SETRQ This bit indicates that the SET_XXXX request to be automatically processed has been received and automatically processed XXXX CONFIGURATION or FEATURE...

Page 295: ...not automatically cleared to 0 even when the CLEAR_FEATURE Endpoint SET_INTERFACE or SET_CONFIGURATION request is received It is not automatically cleared to 0 either if the next SETUP token is receiv...

Page 296: ...zation with the IN token next to the one that set the EP0NKW bit of the UF0E0N register to 1 This bit is automatically set to 1 by hardware when the host correctly receives that data It is also set to...

Page 297: ...is valid for both FW processed and hardware processed requests 1 SETUP token is correctly received interrupt request is generated 0 SETUP token is not received default value This bit is set to 1 when...

Page 298: ...indicates that an IN token has been received in the UF0BI1 register Endpoint 1 and that NAK has been returned 1 IN token is received and NAK is transmitted interrupt request is generated 0 IN token is...

Page 299: ...een received in the UF0BO1 register Endpoint 2 1 Null packet is received interrupt request is generated 0 Null packet is not received default value This bit is set to 1 immediately after reception of...

Page 300: ...ng bit of the UF0IC4 register The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register n 1 2 and the current setting of the interface 0 UF0IS4 0 5 SETINT 0...

Page 301: ...RSU SPDM 5 0 3 0 2 SET RQM 1 CLR RQM EP HALTM Address FF37H After reset 00H 0 4 0 6 7 Bit position Bit name Function 7 BUSRSTM This bit masks the Bus Reset interrupt 1 Mask 0 Do not mask default valu...

Page 302: ...ODTM 6 E0INM 7 0 Bit position Bit name Function 6 E0INM This bit masks the EP0IN interrupt 1 Mask 0 Do not mask default value 5 E0INDTM This bit masks the EP0INDT interrupt 1 Mask 0 Do not mask defaul...

Page 303: ...iting 1 to the corresponding bit of this register The related bits are invalid if each endpoint is not supported by the setting of the UF0E1IM register and the current setting of the interface UF0IM2...

Page 304: ...dpoint is not supported by the setting of the UF0E2IM register and the current setting of the interface 0 UF0IM3 0 5 0 3 BKO1 FLM 2 BKO1 NLM 1 BKO1 NAKM BKO1 DTM Address FF3AH After reset 00H 0 4 0 6...

Page 305: ...nterrupt request INTUSB2B from USBF by writing 1 to the corresponding bit of this register The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register n 1 2 a...

Page 306: ...hardware can be cleared by FW before it is cleared by hardware Writing 0 to a bit of this register automatically sets the bit to 1 Writing 1 is invalid BUS RSTC UF0IC0 RSU SPDC 5 1 3 1 2 SET RQC 1 CL...

Page 307: ...ared by hardware Writing 0 to a bit of this register automatically sets the bit to 1 Writing 1 is invalid UF0IC1 5 E0 INDTC 3 SUCESC 2 STGC 1 PROTC CPU DECC Address FF4BH After reset FFH 0 4 E0ODTC 6...

Page 308: ...omatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware Writing 0 to a bit of this register automatically sets the bit to 1 Writing 1 is invalid The related bits are...

Page 309: ...it is cleared by hardware Writing 0 to a bit of this register automatically sets the bit to 1 Writing 1 is invalid The related bits are invalid if each endpoint is not supported by the setting of the...

Page 310: ...ster Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware Writing 0 to a bit of this register automatically sets the bit to 1 Writing 1 is in...

Page 311: ...SIE side of the UF0BI1 register reset the counter 1 Clear Writing this bit is invalid while an IN token for Endpoint 1 is being processed with the BKI1NK bit set to 1 The BKI1NK bit is automatically c...

Page 312: ...M register and the current setting of the interface 0 UF0FIC1 0 5 0 0 3 0 2 0 1 BKO1C BKO1CC Address FF7AH After reset 00H 0 4 6 7 Bit position Bit name Function 1 BKO1C This bit clears the FIFOs on b...

Page 313: ...0 Do not transmit a short packet default value This bit controls the FIFO on the CPU side If the BKI1CC bit of the UF0FIC0 register is set to 1 and then this bit is set to 1 counter of UF0BI1 registe...

Page 314: ...ame Function 1 CONNECT This bit sets the output level of the USBPUC pin which controls connection of the pull up resistor connected to D 0 USBPUC pin is low level 1 USBPUC pin is high level For the co...

Page 315: ...to 0 If these bits are set to 1 the operation is not guaranteed Caution This register is provided for debugging purposes Usually do not set this register except for verifying the operation or when a s...

Page 316: ...t If this bit is not set to 1 the hardware transfers only the automatically executed request in 8 byte units Therefore even if data of more than 8 bytes is sent by the OUT token to be processed by FW...

Page 317: ...0 0 3 0 2 0 1 IFNO1 IFNO0 Address FF70H After reset 00H 0 4 6 7 Bit position Bit name Function 7 ADDIF This bit allows use of Interfaces numbered other than 0 1 Support up to the Interface number spe...

Page 318: ...range specified by the UF0AIFN register the n series Alternative Setting is invalid ALTnEN bit 0 IFALn1 IFALn0 Interface number to be linked 1 1 Links Interface 4 1 0 Links Interface 3 0 1 Links Inte...

Page 319: ...ASS 0 5 0 0 3 AL5ST3 2 AL5ST2 1 AL5ST1 AL2ST Address FF72H After reset 00H 0 4 6 7 Bit position Bit name Function These bits indicate the current status of the five series Alternative Setting AL5ST3 A...

Page 320: ...Alternative Setting 0 1 0 0 Linked with Interface 3 and Alternative Setting 0 0 1 1 Linked with Interface 2 and Alternative Setting 0 0 1 0 Linked with Interface 1 and Alternative Setting 0 0 0 1 Lin...

Page 321: ...d Alternative Setting 0 1 0 0 Linked with Interface 3 and Alternative Setting 0 0 1 1 Linked with Interface 2 and Alternative Setting 0 0 1 0 Linked with Interface 1 and Alternative Setting 0 0 0 1 Li...

Page 322: ...uest is generated If the reception is abnormal the UF0E0L register is cleared to 0 and the interrupt request is not generated The data held by the UF0E0R register must be read by FW up to the value of...

Page 323: ...access to this register is ignored The UF0E0L register always updates the length of the received data while it is receiving data If the final transfer is abnormal reception the UF0E0L register is cle...

Page 324: ...ile the data of the register is being read Even if the SETUP transaction cannot be correctly received the CPUDEC interrupt request and Protect interrupt request are not generated but the previous data...

Page 325: ...ompletion of decoding request Start of reading FIFO INT clear FW clear Hardware processing b When SETUP transaction is received more than once Status of UF0E0ST register Completion of normal reception...

Page 326: ...EPS0 register 1 data exists A Null packet is transmitted when the UF0E0W register is cleared and the E0DED bit of the UF0DEND register is set to 1 EP0W bit of the UF0EPS0 register 1 data exists The UF...

Page 327: ...r INT clear FW clear Writing FIFO starts Writing FIFO completed Writing FIFO starts Writing FIFO completed Counter reloaded Hardware clear Hardware clear b When Null packet or short packet is transmit...

Page 328: ...to the value of the amount of data read by the UF0BO1L register When the correct received data is held by the FIFO connected to the SIE side and the value of the UF0BO1L register reaches 0 the toggle...

Page 329: ...ission Reception starts Reception completed ACK transmission BKO1NK bit of UF0EN register BKO1FL bit of UF0IS3 register BKOUT1 bit of UF0EPS0 register BKO1DT bit of UF0IS3 register Transfer of data le...

Page 330: ...tion completed FIFO toggle FIFO toggle ACK transmission Reception starts Reception completed ACK transmission BKO1NL bit of UF0IS3 register BKOUT1 bit of UF0EPS0 register BKO1DT bit of UF0IS3 register...

Page 331: ...0BO1L register is cleared to 00H and an interrupt request is not generated Only if the reception is normal the interrupt request is generated and FW can read as much data from the UF0BO1 register as t...

Page 332: ...a is to be written or read is managed by the hardware Therefore FW can transmit data to the host only by writing the data to the UF0BI1 register sequentially A short packet is transmitted when data is...

Page 333: ...ansmission completed ACK reception BKI1NK bit of UF0EN register 64 byte transfer 64 byte transfer FIFO_0 FIFO_1 FIFO_1 FIFO_0 Writing FIFO starts Writing FIFO completed Writing FIFO starts Writing FIF...

Page 334: ...CK reception Transmission starts Transmission completed ACK reception Re transmission starts ACK cannot be received BKI1NK bit of UF0EN register 64 byte transfer Re transfer 64 byte transfer FIFO_0 FI...

Page 335: ...ion Transmission starts Transmission completed ACK reception BKI1NK bit of UF0EN register Transfer of Null packet Short packet transfer 64 byte transfer FIFO_0 FIFO_1 FIFO_1 FIFO_0 FIFO clear Writing...

Page 336: ...t in order to prevent conflict between a read access and a write access 0 UF0DSTL 0 5 0 0 3 0 2 0 1 RMWK SFPW Address FF9AH After reset 00H 0 4 6 7 Bit position Bit name Function 1 RMWK This bit speci...

Page 337: ...est The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint0 request If Endpoint0 has stalled the UF0E0W and UF0E0R registers are cl...

Page 338: ...r is always masked when transfer to Endpoint1 rather than control transfer is executed be sure to check this register to see if data has been correctly written to it Caution To rewrite this register s...

Page 339: ...r is always masked when transfer to Endpoint2 rather than control transfer is executed be sure to check this register to see if data has been correctly written to it Caution To rewrite this register s...

Page 340: ...f the SET_ADDRESS request is processed by FW the value of this register is reflected as the device address when the SUCCESS signal is received in the status stage Caution Do not perform write access t...

Page 341: ...NF bits of UF0MODS register are set to 1 If the SET_CONFIGURATION request is processed by FW the status of this register is immediately reflected on the UF0MODS register as soon as data has been writt...

Page 342: ...and wValue are decoded and the setting of endpoint is automatically changed At this time the status bit of the target endpoint and DPID are automatically cleared to 0 depending on the setting The FIFO...

Page 343: ...e are decoded and the setting of endpoint is automatically changed At this time the status bit of the target endpoint and DPID are automatically cleared to 0 depending on the setting The FIFO is not c...

Page 344: ...means that the descriptor to be returned is 1 byte long If the register is set to FFH a descriptor length of 256 bytes is returned When a descriptor exceeding 256 bytes in length is used set the CDCG...

Page 345: ...ontents UF0DD0 F9D1H bLength Size of this descriptor UF0DD1 F9D2H bDescriptorType Device descriptor type UF0DD2 F9D3H Value below decimal point of Rev number of USB specification UF0DD3 F9D4H bcdUSB V...

Page 346: ...e descriptor 9 bytes F9F5H Endpoint1 descriptor 7 bytes F9FCH Endpoint2 descriptor 7 bytes FA03H FAxxH Interface descriptor 9 bytes FAxxH 9 Endpoint1 descriptor 7 bytes FAxxH 16 Endpoint2 descriptor 7...

Page 347: ...this Configuration unit mA Note Note This value is expressed in 2mA units example 50 100 mA b Interface descriptor 9 bytes Offset Field Name Contents 0 bLength Size of this descriptor 1 bDescriptorTyp...

Page 348: ...USB buffer 1 Buffer valid 0 Buffer invalid Caution Clear this bit to 0 when the USB is not used If this bit is set to 1 a current of 3 mA TYP constantly flows regardless of whether the USB is used or...

Page 349: ...Then Reconnected Checks status of pin interrupt detecting host connection status Masks INTUSBnB and INTRSUM interrupts Disables USE bus enables measures against floating Yes Host disconnected No STAR...

Page 350: ...clock supply START Enables USE bus disables measures against floating END Checks status of pin interrupt detecting host connection status Initializes register area enables measures against floating U...

Page 351: ...NDSTL bit of UF0SDS register to 1 and discard received data Bulk transfer OUT Data Overrun No response Note 1 Set EnHALT bit of UF0EnSL register n 0 to 2 to 1 PID check error Hold transferred data and...

Page 352: ...F0IS3 register 00H Value is held UF0IS4 register 00H Value is held UF0IM0 register 00H Value is held UF0IM1 register 00H Value is held UF0IM2 register 00H Value is held UF0IM3 register 00H Value is he...

Page 353: ...UF0CNF register 00H 00H UF0IF0 register 00H 00H UF0IF1 register 00H 00H UF0IF2 register 00H 00H UF0IF3 register 00H 00H UF0IF4 register 00H 00H UF0DSCL register 00H Value is held UF0DDn register n 0 t...

Page 354: ...URE and CLEAR_FEATURE requests during enumeration processing Analysis and processing of XXXXStandard XXXXClass and XXXXVendor requests not subject to automatic processing Reading data following bulk t...

Page 355: ...OR Device FW Rewrites the device descriptor When this request is received by the SETUP token the hardware generates the CPUDEC interrupt request for FW FW decodes the contents of the request from the...

Page 356: ...can be masked by using the UF0IMn register n 0 to 4 The following flowcharts illustrate the above processing Figure 12 9 Initializing Request Data Register START END EP0NKA 1 UF0E0NA Cancels NAK respo...

Page 357: ...ster Inputting UF0DDm register Inputting UF0CIEa register Remark m 0 to 17 a 0 to 255 Figure 12 11 Setting of Interface and Endpoint ADDIF IFNO1 IFNO0 000 Interface number 0 is valid ADDIF IFNO1 IFNO0...

Page 358: ...Figure 12 12 Setting of Interrupt START END Mask the interrupt source to avoid issuance of an unnecessary interrupt request INTUSBmB Setting of UF0IMn register Remark n 0 to 4 m 0 where n 0 1 m 1 wher...

Page 359: ...ter Target bit of UF0ICm register 0 Servicing interrupt Masking ID bit Remark Processing by hardware The following bits of the UF0ISn register are automatically cleared by hardware when a given condit...

Page 360: ...ed request for control transfer Because the fully automatically processed request for control transfer is executed by hardware it cannot be referenced by FW Therefore FW does not have to perform any s...

Page 361: ...t CPUDEC processing Illegal processing Illegal processing Yes No INTUSB2B 1 Reading UF0ISn register Reading UF0IS4 register Reading UF0SET register FW processing for each request Yes Yes No No CLRRQ 1...

Page 362: ...ponding bit for the value of 0XH The EPHALT bit of the UF0IS0 register is cleared to 0 only when all Halt Features are cleared UF0CLR register 0XH CLRRQ 1 UF0IS0 HALTn 0 UF0EPS2 Clearing UF0DSTL regis...

Page 363: ...ing bit for the value of 0XH The EPHALT bit of the UF0IS0 register is not set to 1 by setting the UF0DSTL register UF0SET register 0XH SETRQ 1 UF0IS0 HALTn 1 UF0EPS2 EPHALT 1 UF0IS0 Setting UF0DSTL re...

Page 364: ...ocessing SETCON 1 UF0SET SETRQ 1 UF0IS0 CONF 1 UF0MODS Setting UF0CNF register Remark Processing by hardware Figure 12 18 SET_INTERFACE Processing SETINT 1 UF0IS4 Setting UF0ASS register Setting UF0IF...

Page 365: ...dicates a request that uses the IN transaction in the data stage e g GET_DESCRIPTOR Control transfer without data indicates a request that has no data stage e g SET_CONFIGURATION The flowcharts are sh...

Page 366: ...es No SETUP token received Yes No STALL handshake response END E C D A In the case of an unsupported request for control transfer write clear the FIFO because data may be written to the FIFO as a resu...

Page 367: ...Transmitting NAK E0IN 1 UF0IS1 Writing UF0E0W register E0INM 1 UF0IM1 Yes No Yes No B If return data greater than the FIFO size exists it is divided into FIFO size units and sequentially written star...

Page 368: ...Control Transfer 4 12 b Control transfer read 2 4 FIFO full E0DED 1 UF0DEND EP0NKW 1 UF0E0N Transmitting data of UF0E0W register Yes No IN token received Yes No PROT 1 UF0IS1 No Yes G H ACK received Y...

Page 369: ...Control transfer read 3 4 I J No transmit data E0INDT 1 UF0IS1 EP0NKW 0 UF0E0N E0INDTC 0 UF0IC1 STG 1 UF0IS1 Yes Yes No H INTUSB0B active Reading UF0ISn register E0INDT 1 UF0IS1 No Yes Data of Null p...

Page 370: ...0B active Reading UF0ISn register Reading UF0ISn register Transmitting ACK INTUSB0B active CPUDECM 0 UF0IM1 E0INM 0 UF0IM1 Yes STG 1 UF0IS1 No Yes SUCES 1 UF0IS1 No STGM 1 UF0IM1 SUCES 1 UF0IS1 SUCESC...

Page 371: ...ransfer write 1 4 Clearing UF0E0R register C K G INTUSB0B active Yes Normal reception No EP0RC 1 UF0FIC0 No PROT 1 UF0IS1 Yes Yes OUT token received No Writing UF0E0R register E0ODT 1 UF0IS1 EP0R 1 UF...

Page 372: ...UF0EPS0 EP0NKR 0 UF0E0N Yes IN token received No Yes E0ODT 1 UF0IS1 No Reading UF0E0R register Data length Data length 1 No Data length other than 0 Yes Updating data length of UF0E0L register Updatin...

Page 373: ...2 c Control transfer write 3 4 L INTUSB0B active Yes STG 1 UF0IS1 No STG 1 UF0IS1 E0IN 1 UF0IS1 Reading UF0ISn register G Clearing read data No PROT 1 UF0IS1 Yes Request processing EP0WC 1 UF0FIC0 E0D...

Page 374: ...eived No Yes SUCES 1 UF0IS1 No INTUSB0B active Transmitting data of Null packet Reading UF0ISn register SUCES 1 UF0IS1 E0INDT 1 UF0IS1 SUCESC 0 UF0IC1 E0INDTC 0 UF0IC1 E0INC 0 UF0IC1 CPUDECM 0 UF0IM1...

Page 375: ...ut data stage 1 2 D Yes STG 1 UF0IS1 No Yes IN token received No E0DED 1 UF0DEND E0IN 1 UF0IS1 STG 1 UF0IS1 INTUSB0B active Reading UF0ISn register EP0WC 1 UF0FIC0 G Request processing aborted No PROT...

Page 376: ...ed No Yes SUCES 1 UF0IS1 No INTUSB0B active Transmitting data of Null packet Reading UF0ISn register SUCES 1 UF0IS1 E0INDT 1 UF0IS1 SUCESC 0 UF0IC1 E0INC 0 UF0IC1 E0INDTC 0 UF0IC1 E0INM 0 UF0IM1 CPUDE...

Page 377: ...NTROLLER USBF Preliminary User s Manual U19014EJ1V0UD 377 4 Processing for bulk transfer IN Bulk transfer IN is allocated to Endpoint1 The flowchart is shown below Downloaded from Elcodis com electron...

Page 378: ...2 register BKI1INC 0 UF0IC2 BKI1DTC 0 UF0IC2 BKI1INM 0 UF0IM2 Data error Reading UF0IS2 register Writing UF0BI1 register BKI1NK 1 UF0EN BKI1DT 1 UF0IS2 BKI1INM 1 UF0IM2 If return data greater than the...

Page 379: ...4EJ1V0UD 379 Figure 12 21 Parallel Processing by Hardware Yes Yes IN token received No Transmitting data of UF0BI1 register ACK received No Yes No transmit data No BKI1NK 0 UF0EN Remark Processing by...

Page 380: ...TROLLER USBF Preliminary User s Manual U19014EJ1V0UD 380 5 Processing for bulk transfer OUT Bulk transfer OUT is allocated to Endpoint2 The flowchart is shown below Downloaded from Elcodis com electro...

Page 381: ...EPS0 Clearing UF0BO1 register Yes No Normal reception INTUSB1B active Reading UF0IS3 register BKO1DT 0 UF0IS3 BKOUT1 0 UF0EPS0 Updating data length of UF0BO1L register Reading UF0BO1 register Data len...

Page 382: ...ta can be read from the CPU side even while the bus side is being accessed as the transfer rate of the USB bus increases Consequently if the host sends more data than expected by the system up to 128...

Page 383: ...TART Writing UF0BO1 register BKO1DT 1 UF0IS3 BKOUT1 1 UF0EPS0 INTUSB1B active Clearing UF0BO1 register Yes Normal reception No Writing UF0BO1 register Reading UF0ISn register BKO1NKM 1 UF0ENM BKO1FL 1...

Page 384: ...F0ENM BKO1NK 0 UF0EN BKO1NAKC 0 UF0IC3 Yes BKO1NAK 1 UF0IS3 No END END Reading UF0BO1 register BKO1FL 0 UF0IS3 Reading UF0BO1 register Data length Data length 1 No Data length other than 0 Yes UF0BO1...

Page 385: ...Figure 12 24 Example of Suspend Resume Processing 1 3 a Example of Suspend processing RSUSPD 1 UF0IS0 RSUM 1 UF0EPS1 Yes Suspend detected No Yes RSUSPD 1 UF0IS0 No Yes RSUM 1 UF0EPS1 No START END INTU...

Page 386: ...cessing RSUSPD 1 UF0IS0 RSUM 0 UF0EPS1 Yes Resume detected No Yes RSUSPD 1 UF0IS0 No Yes RSUM 0 UF0EPS1 No START END INTUSB0B active Reading UF0ISn register Reading UF0EPS1 register FW Resume processi...

Page 387: ...end Resume Processing 3 3 c Example of Resume processing when supply of USB clock to USBF is stopped INTRSUM active Yes Resume detected No START END Executing interrupt servicing Supplying USB clock F...

Page 388: ...essing of D activeNote 1 Connection Controlling portNote 2 BUSRST 1 UF0IS0 DFLT 1 UF0MODS Initialization of request data register Initialization of request data register See Figure 12 10 Initializatio...

Page 389: ...K 1 UF0MODS Receiving SET_ADDRESS request Writing to UF0ADRS register Receiving SET_CONFIGURATION 1 request Receiving SET_INTERFACE request Processing continues SETCON 1 UF0SET SETRQ 1 UF0IS0 CONF 1 U...

Page 390: ...ternal interrupt pin of the PD78F0730 INTP0 to INTP3 Allocate one external interrupt pin to the following applications Detecting disconnection of the connector in the case of self powered mode SFPW bi...

Page 391: ...host HUB such as while higher priority processing or initialization processing is under execution the system must control pull up of D via the USBPUC pin In the circuit example in Figure 12 26 D is p...

Page 392: ...ted then they are processed according to the priority of vectored interrupt servicing For the priority order see Table 13 1 A standby release signal is generated and STOP and HALT modes are released E...

Page 393: ...when compare register is specified TI010 pin valid edge detection when capture register is specified 0020H 15 INTTM010 Match between TM00 and CR010 when compare register is specified TI000 pin valid e...

Page 394: ...errupt INTP0 to INTP3 Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal External interrupt edge enable register EGP EGN Edge dete...

Page 395: ...ags corresponding to interrupt request sources Table 13 2 Flags Corresponding to Interrupt Request Sources Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Interrupt Source Regis...

Page 396: ...generation sets these registers to 00H Figure 13 2 Format of Interrupt Request Flag Registers IF0L IF0H IF1L IF1H Address FFE0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0L SREIF6 USBIF1 USBIF2 PI...

Page 397: ...nipulation instructions CLR1 If an 8 bit memory manipulation instruction IF0L 0xfe is described in C language for example it is converted to the following three assembly instructions after compilation...

Page 398: ...FFH Figure 13 3 Format of Interrupt Mask Flag Registers MK0L MK0H MK1L MK1H Address FFE4H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0L SREMK6 USBMK1 USBMK0 PMK3 PMK2 PMK1 PMK0 LVIMK Address FFE5H A...

Page 399: ...e registers to FFH Figure 13 4 Format of Priority Specification Flag Registers PR0L PR0H PR1L PR1H Address FFE8H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L SREPR6 USBPR1 USBPR0 PPR3 PPR2 PPR1 PPR...

Page 400: ...P0 Address FF49H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN 0 0 0 0 EGN3 EGN2 EGN1 EGN0 EGPn EGNn INTPn pin valid edge selection n 0 to 3 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising ed...

Page 401: ...is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag The PSW contents are also sa...

Page 402: ...hen PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time becomes longer Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskable interru...

Page 403: ...est held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Vectored interrupt servicing Any high priority interrupt request among those simultaneousl...

Page 404: ...essing IF PR 1 IF PR 0 6 clocks 25 clocks Remark 1 clock 1 fCPU fCPU CPU clock 13 4 2 Software interrupt request acknowledgement A software interrupt acknowledge is acknowledged by BRK instruction exe...

Page 405: ...nerated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because the...

Page 406: ...st always be issued to enable interrupt request acknowledgment Example 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing INTxx PR 0...

Page 407: ...RETI INTxx PR 0 INTyy PR 0 IE 0 IE 0 IE 1 IE 1 Interrupts are not enabled during servicing of interrupt INTxx EI instruction is not issued therefore interrupt request INTyy is not acknowledged and mul...

Page 408: ...1H PR0L PR0H PR1L and PR1H registers Caution The BRK instruction is not one of the above listed interrupt request hold instructions However the software interrupt activated by executing the BRK instru...

Page 409: ...system thereby considerably reducing the CPU operating current Because this mode can be cleared by an interrupt request it enables intermittent operations to be carried out However because a wait time...

Page 410: ...0 0 0 2 11 fX min 170 7 s min 128 s min 1 1 0 0 0 2 13 fX min 682 7 s min 512 s min 1 1 1 0 0 2 14 fX min 1 37 ms min 1 024 msmin 1 1 1 1 0 2 15 fX min 2 73 ms min 2 048 ms min 1 1 1 1 1 2 16 fX min 5...

Page 411: ...MHz 0 0 1 2 11 fX 170 7 s 128 s 0 1 0 2 13 fX 682 7 s 512 s 0 1 1 2 14 fX 1 37 ms 1 024 ms 1 0 0 2 15 fX 2 73 ms 2 048 ms 1 0 1 2 16 fX 5 46 ms 4 096 ms Other than above Setting prohibited Cautions 1...

Page 412: ...mode The HALT mode is set by executing the HALT instruction HALT mode can be set regardless of whether the CPU clock before the setting was the high speed system clock or internal high speed oscillat...

Page 413: ...by external clock input Operation continues cannot be stopped fRL Status before HALT mode was set is retained PLL Operable CPU Operation stopped Flash memory Operation stopped RAM Status before HALT m...

Page 414: ...is executed Figure 14 3 HALT Mode Release by Interrupt Request Generation HALT instruction Wait Wait Operating mode HALT mode Operating mode Oscillation High speed system clock or internal high speed...

Page 415: ...al operation high speed system clock Oscillation stabilization time 211 fX to 216 fX Normal operation internal high speed oscillation clock Oscillation stopped Starting X1 oscillation is specified by...

Page 416: ...cuting the STOP instruction and it can be set only when the CPU clock before the setting was the main system clock Caution Because the interrupt request signal is used to clear the standby mode if the...

Page 417: ...e was set is retained 16 bit timer event counter 00 Operation stopped 50 Operable only when TI50 is selected as the count clock 8 bit timer event counter 51 Operable only when TI51 is selected as the...

Page 418: ...xternal main system clock is used as the CPU clock the internal high speed oscillation clock or external main system clock is supplied to the CPU 5 s MIN after the STOP mode has been released 2 STOP m...

Page 419: ...cillates Oscillates STOP instruction STOP mode Wait set by OSTS Standby release signal Oscillation stabilization wait HALT mode status Oscillation stopped High speed system clock X1 oscillation Status...

Page 420: ...ied by software Oscillation stopped Reset processing 20 s TYP 2 When internal high speed oscillation clock is used as CPU clock STOP instruction Reset signal Internal high speed oscillation clock Norm...

Page 421: ...t to the RESET pin the device is reset It is released from the reset status when a high level is input to the RESET pin and program execution is started with the internal high speed oscillation clock...

Page 422: ...reset signal RESET Power on clear circuit reset signal Low voltage detector reset signal Reset signal Reset signal to LVIM LVIS register Clear Set Clear Set Caution An LVI circuit internal reset does...

Page 423: ...oscillation is specified by software Reset processing 20 s TYP Figure 15 3 Timing of Reset Due to Watchdog Timer Overflow Normal operation Reset period oscillation stop CPU clock Watchdog timer overf...

Page 424: ...ck when X1 oscillation is selected Internal high speed oscillation clock Hi Z Port pin Starting X1 oscillation is specified by software Normal operation internal high speed oscillation clock Reset pro...

Page 425: ...Flash memory RAM Operation stopped For chip Regulator For USB Operable Port latch 16 bit timer event counter 00 50 8 bit timer event counter 51 8 bit timer H1 Watchdog timer UART6 CSI10 Serial interfa...

Page 426: ...register UCKC 00H Timer counter 00 TM00 0000H Capture compare registers 000 010 CR000 CR010 0000H Mode control register 00 TMC00 00H Prescaler mode register 00 PRM00 00H Capture compare control regis...

Page 427: ...EPNAK register UF0EN 00H UF0 EPNAK mask register UF0ENM 00H UF0 SNDSIE register UF0SDS 00H UF0 CLR request register UF0CLR 00H UF0 SET request register UF0SET 00H UF0 EP status n register UF0EPSn n 0...

Page 428: ...Reset function Reset control flag register RESF 00H Note 2 Low voltage detection register LVIM 00H Note 2 Low voltage detector Low voltage detection level selection register LVIS 00H Note 2 Request fl...

Page 429: ...RF WDTRF Internal reset request by watchdog timer WDT 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated LVIRF Internal reset request by low voltage det...

Page 430: ...D78F0730 be sure to set the 2 7 V 1 59 V POC mode by using the option byte POCMODE 1 Caution If an internal reset signal is generated in the POC circuit the reset control flag register RESF is cleared...

Page 431: ...1 59 V POC mode option byte POCMODE 1 An internal reset signal is generated on power application When the supply voltage VDD exceeds the detection voltage VDDPOC 2 7 V 0 2 V the reset status is relea...

Page 432: ...n accuracy stabilization Wait for oscillation accuracy stabilization Wait for oscillation accuracy stabilization Reset processing 20 s TYP Reset processing 20 s TYP Reset processing 20 s TYP Set LVI t...

Page 433: ...er and then initialize the ports Figure 16 3 Example of Software Processing After Reset Release 1 2 If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Check the reset...

Page 434: ...essing After Reset Release 2 2 Checking reset source Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector No WD...

Page 435: ...is used to reset bit 0 LVIRF of the reset control flag register RESF is set to 1 if reset occurs For details of RESF see CHAPTER 15 RESET FUNCTION 17 2 Configuration of Low Voltage Detector The block...

Page 436: ...gisters Controlling Low Voltage Detector The low voltage detector is controlled by the following registers Low voltage detection register LVIM Low voltage detection level selection register LVIS Port...

Page 437: ...e VDD detection voltage VLVI LVIF Note 4 Low voltage detection flag 0 Supply voltage VDD detection voltage VLVI or when operation is disabled 1 Supply voltage VDD detection voltage VLVI Notes 1 Bit 0...

Page 438: ...LVI1 4 09 V 0 1 V Cautions 1 Be sure to clear bits 1 to 7 to 0 2 Do not change the value of LVIS during LVI operation 3 Port mode register 12 PM12 When using the P120 INTP0 pin for external low voltag...

Page 439: ...two modes 1 Used as reset Compare the supply voltage VDD and detection voltage VLVI generate an internal reset signal when VDD VLVI and releases internal reset when VDD VLVI 2 Used as interrupt Compa...

Page 440: ...o 1 generates internal reset signal when supply voltage VDD detection voltage VLVI Figure 17 5 shows the timing of the internal reset signal generated by the low voltage detector The numbers in this t...

Page 441: ...ared by software 3 6 Clear Clear Clear 4 Wait time LVION flag set by software LVIMD flag set by software HNote 1 5 2 7 V TYP VPOC 1 59 V TYP Notes 1 The LVIMK flag is set to 1 by reset signal generati...

Page 442: ...LVIM 6 Clear the interrupt request flag of LVI LVIIF to 0 7 Release the interrupt mask flag of LVI LVIMK 8 Clear bit 1 LVIMD of LVIM to 0 generates interrupt signal when supply voltage VDD detection v...

Page 443: ...it time LVION flag set by software Note 2 Note 2 2 LVIMD flag set by software L 8 VLVI 2 7 V TYP VPOC 1 59 V TYP Note 2 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The interrupt re...

Page 444: ...below In this system take the following actions Action 1 When used as reset After releasing the reset signal wait for the supply voltage fluctuation period of each system by means of a software counte...

Page 445: ...MIFH1 1 Initialization processing 2 Setting 8 bit timer H1 to measure 50 ms Setting of division ratio of system clock such as setting of timer Yes No Setting LVI Clearing WDT Detection voltage or high...

Page 446: ...ssing After Reset Release 2 2 Checking reset source Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector Yes WD...

Page 447: ...TYP It is released from the reset state when the voltage exceeds 2 7 V TYP After that POC is not detected at 2 7 V but is detected at 1 59 V TYP During 1 59 V POC mode operation POCMODE 0 The device i...

Page 448: ...l low speed oscillator operation 0 Can be stopped by software stopped when 1 is written to bit 0 LSRSTOP of RCM register 1 Cannot be stopped not stopped even if 1 is written to LSRSTOP bit Note Set a...

Page 449: ...o bit 0 and be sure to clear bits 7 to 1 to 0 Address 0082H 1082H 0083H 1083H Note 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Note Be sure to set 00H to 0082H and 0083H as these addresses are reserved areas Also...

Page 450: ...Window open period of watchdog timer 100 Overflow time of watchdog timer 210 fRL Internal low speed oscillator can be stopped by software DB 01H 2 7 1 59 V POC mode DB 00H Reserved area DB 00H Reserve...

Page 451: ...mory manipulation instruction Reset signal generation sets IMS to CFH Caution Be sure to set IMS to C4H after a reset release Figure 19 1 Format of Internal Memory Size Switching Register IMS Address...

Page 452: ...instruction Reset signal generation sets IXS to 0CH Caution Be sure to set to 08H after a reset release Figure 19 2 Format of Internal Expansion RAM Size Switching Register IXS Address FFF4H After re...

Page 453: ...I O Pin Function Pin Name Pin No Pin Name Pin No SI RxD Input Receive signal SO10 P12 28 TxD6 P13 27 SO TxD Output Transmit signal SI10 P11 29 RxD6 P14 26 SCK Output Transfer clock SCK10 P10 30 CLK Ou...

Page 454: ...ory writing are shown below Figure 19 3 Example of Wiring Adapter for Flash Memory Writing in 3 Wire Serial I O CSI10 Mode 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14...

Page 455: ...12 13 17 14 15 VDD2 VDD GND SI SO SCK CLK RESET FLMD0 WRITER INTERFACE VDD 4 5 to 5 5 V GND Note Note Note The above figure illustrates an example of wiring when using the clock output from the PG FP...

Page 456: ...flash memory programmer and the PD78F0730 CSI10 or UART6 is used for manipulation such as writing and erasing To write the flash memory off board a dedicated program adapter FA series is necessary 19...

Page 457: ...Signal Name I O Pin Function Pin Name CSI10 UART6 FLMD0 Output Mode signal FLMD0 VDD I O VDD voltage generation power monitoring VDD EVDD GND Ground VSS EVSS CLK Output Clock output to PD78F0730 Note...

Page 458: ...FLMD0 pin In the flash memory programming mode the VDD write voltage is supplied to the FLMD0 pin An FLMD0 pin connection example is shown below Figure 19 8 FLMD0 Pin Connection Example VDD EVDD VSS E...

Page 459: ...e other device PD78F0730 2 Malfunction of other device If the dedicated flash memory programmer output or input is connected to a pin input or output of a serial interface connected to another device...

Page 460: ...evices connected to the ports do not recognize the port status immediately after reset the port pin must be connected to VDD or VSS via a resistor 19 6 5 REGC pin Connect the REGC pin to GND via a cap...

Page 461: ...ion with the flash memory programmer To use the on board supply voltage connect in compliance with the normal operation mode Supply the same other power supplies EVDD and EVSS as those in the normal o...

Page 462: ...the FLMD0 pin to VDD and clear the reset signal Change the mode by using a jumper when writing the flash memory on board Figure 19 13 Flash Memory Programming Mode VDD RESET 5 5 V 0 V VDD 0 V Flash m...

Page 463: ...n Mode Port Speed Frequency Multiply Rate Pins Used Peripheral Clock Number of FLMD0 Pulses UART Ext Osc fX 0 UART UART6 UART Ext FP4CK 115 200 bps 16 MHz TxD6 RxD6 fEXCLK 3 3 wire serial I O CSI10 CS...

Page 464: ...data transmitted from the programmer Chip Erase Erases the entire flash memory Erase Block Erase Erases a specified area in the flash memory Blank check Block Blank Check Checks if a specified block...

Page 465: ...k erase Execution of the block erase command for a specific block in the flash memory is prohibited during on board off board programming However blocks can be erased by means of self programming Disa...

Page 466: ...hibition of writing Blocks can be erased Can be performed Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased Boot cluster 0 cannot be written Table 19 9 shows how to perform secur...

Page 467: ...lf programming is stopped 3 Self programming is also stopped by an interrupt request that is not masked even in the DI status To prevent this mask the interrupt by using the interrupt mask flag regist...

Page 468: ...High level Normal completion Yes No Setting operating environment FlashEnv CheckFLMD FlashBlockBlankCheck Erased Yes Yes No FlashBlockErase Normal completion FlashWordWrite Normal completion FlashBlo...

Page 469: ...the program is reset and started next If the program has been correctly written to boot cluster 0 restore the original boot area by using the set information function of the firmware of the PD78F0730...

Page 470: ...program New boot program New boot program New boot program New boot program Boot program 3 2 1 0 7 6 5 4 Boot program Boot program Boot program New boot program New boot program New boot program New...

Page 471: ...f rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed NEC Electronics is not liable for problems occurring when the o...

Page 472: ...8K0MINI target connector FLMD0 FLMD0 PD78F0730 Port 1 k recommended 10 k recommended 20 1 On Chip Debug Security ID The PD78F0730 has an on chip debug operation control flag in the flash memory at 008...

Page 473: ...rite the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for specification Tabl...

Page 474: ...iliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag Memory contents indicated by address or register contents in parentheses XH XL Higher 8 bits and lower 8 bi...

Page 475: ...byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C MOV HL C A 1 6 7 HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 A addr16 A...

Page 476: ...CY A HL A HL byte 2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B ADD A HL C 2 8 9 A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r...

Page 477: ...Y A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY SUBC A HL C 2 8 9 A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A...

Page 478: ...4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B XOR A HL C 2 8 9 A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9...

Page 479: ...HL 7 4 Rotate ROL4 HL 2 10 12 A3 0 HL 7 4 HL 3 0 A3 0 HL 7 4 HL 3 0 ADJBA 2 4 Decimal Adjust Accumulator after Addition BCD adjustment ADJBS 2 4 Decimal Adjust Accumulator after Subtract CY saddr bit...

Page 480: ...CY CY PSW bit XOR1 CY HL bit 2 6 7 CY CY HL bit saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 SET1 HL bit 2 6 8 HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bi...

Page 481: ...SP 2 rpL SP SP 2 PSW 1 2 PSW SP SP SP 1 R R R POP rp 1 4 rpH SP 1 rpL SP SP SP 2 SP word 4 10 SP word SP AX 2 8 SP AX Stack manipulate MOVW AX SP 2 8 AX SP addr16 3 6 PC addr16 addr16 2 6 PC PC 2 jdis...

Page 482: ...then reset sfr bit A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit BTCLR HL bit addr16 3 10 12 PC PC 3 jdisp8 if HL bit...

Page 483: ...ND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MO...

Page 484: ...W MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 None A bit...

Page 485: ...BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand AX addr16 addr11 addr5 addr16 Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ 5 Other in...

Page 486: ...ltage EVSS 0 5 to 0 3 V VI1 P00 P01 P10 to P17 P30 to P33 P120 to P122 X1 X2 RESET EXCLK FLMD0 0 3 to VDD 0 3 Note1 V VI2 P60 P61 N ch open drain 0 3 to 6 5 V VI3 USBP USBM 0 5 to 3 8 VI4 REGC 0 5 to...

Page 487: ...the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute ma...

Page 488: ...nal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor to a ground pattern through which...

Page 489: ...ternal oscillator Internal high speed oscillation clock frequency fRH Note 1 RSTS 0 VDD 2 7 V 2 48 5 6 9 86 MHz 240 kHz internal oscillator Internal low speed oscillation clock frequency fRL 2 7 V VDD...

Page 490: ...DD 5 5 V 400 A Notes 1 Value of current at which the device operation is guaranteed even if the current flows from VDD to an output pin 2 Value of current at which the device operation is guaranteed e...

Page 491: ...USBM 0 0 8 V VOH1 P00 P01 P10 to P17 P30 to P33 P120 4 0 V VDD 5 5 V IOH 3 0 mA VDD 0 7 V VOH2 P121 P122 IOH 100 A VDD 0 5 V VOH3 USBP USBM RL 15 k VSS connected 2 8 3 6 V Output voltage high VOH4 US...

Page 492: ...erating mode fXP 16 MHz VDD 5 0 V 17 5 33 mA Supply current Note 2 IDD3 Note 5 STOP mode VDD 5 0 V 2 6 38 A Notes 1 Voltage output to the USBREGC pin 3 3 V 0 3 V 2 Total current flowing into the inter...

Page 493: ...vel width low level width tEXCLKH tEXCLKL 1 fEXCLK 1 2 1 ns TI000 TI010 input high level width low level width tTIH0 tTIL0 4 0 V VDD 5 5 V 2 fsam 0 1 Note s TI50 TI51 input frequency fTI5 4 0 V VDD 5...

Page 494: ...3 0 4 0 5 0 6 0 5 5 2 7 20 0 2 6 0 01 Supply voltage VDD V Cycle time T CY s Guaranteed operation range AC Timing Test Points except Excluding External Main System Clock input 0 8VDD 0 2VDD Test poin...

Page 495: ...inary User s Manual U19014EJ1V0UD 495 TI Timing TI000 TI010 tTIL0 tTIH0 TI50 TI51 1 fTI5 tTIL5 tTIH5 Interrupt Request Input Timing INTP0 to INTP3 tINTL tINTH RESET Input Timing RESET tRSL Downloaded...

Page 496: ...ime to SCK10 tSIK1 70 ns SI10 hold time from SCK10 tKSI1 30 ns Delay time from SCK10 to SO10 output tKSO1 C 50 pF Note 2 40 ns Notes 1 This value is when high speed system clock fXH is used 2 C is the...

Page 497: ...IONS TARGET Preliminary User s Manual U19014EJ1V0UD 497 Serial Transfer Timing CSI10 SI10 SO10 tKCYm tKLm tKHm tSIKm tKSIm Input data tKSOm Output data SCK10 Remark m 1 2 Downloaded from Elcodis com e...

Page 498: ...ange inclination of VPOC 0 75 V ms Minimum pulse width tPW When the supply voltage VDD drops 200 s POC Circuit Timing Supply voltage VDD Time Detection voltage MIN Detection voltage TYP Detection volt...

Page 499: ...pply voltage level VLVI1 LVIS0 1 3 99 4 09 4 19 V Minimum pulse width tLW 200 s Operation stabilization wait time Note tLWAIT 10 s Note Time required from setting bit 7 LVION of the low voltage detect...

Page 500: ...2 0 V Notes 1 Voltage output to the USBREGC pin 2 CL is the load capacitance of the USBM and USBP output lines USBF Timing USBP USBM TBP TF TR VCRS Data Memory STOP Mode Low Supply Voltage Data Retent...

Page 501: ...15 years 1 erase 1 write after erase 1 rewrite Note 3 100 Times Notes 1 These are characteristics of the flash memory These characteristic are not the rewrite time by a dedicated flash programmer PG F...

Page 502: ...true position T P at maximum material condition ITEM DIMENSIONS A B C E F G H I J L M N D 0 30 0 65 T P 0 10 0 05 1 30 0 10 1 20 8 10 0 20 6 10 0 10 1 00 0 20 0 50 0 13 0 10 0 22 0 10 0 05 K 0 15 0 0...

Page 503: ...g until the correct data is passed As a result the CPU does not start the next instruction processing but waits If this happens the number of execution clocks of an instruction increases by the number...

Page 504: ...guration Support for PC98 NX series Unless otherwise specified products supported by IBM PC ATTM compatibles are compatible with PC98 NX series computers When using PC98 NX series computers refer to t...

Page 505: ...sh memory programming adapter Flash memory Software package Project manager Software package Flash memory programming environment Control software Windows only Note 2 Power supply unit USB interface c...

Page 506: ...Target connector Target system Flash memory programmer Flash memory programming adapter Flash memory Software package Project manager Software package Flash memory programming environment Control soft...

Page 507: ...mpiler converts programs written in C language into object codes executable with a microcontroller This compiler should be used in combination with an assembler package and device file both sold separ...

Page 508: ...gram such as starting the editor building and starting the debugger can be performed from the project manager Caution The project manager is included in the assembler package RA78K0 It can only be use...

Page 509: ...5A4 type QB 30MC HQ 01T Mount adapter This mount adapter is used to mount the target device with socket QB 30MC HQ 01T 30 pin plastic SSOP MC 5A4 type QB 30MC NQ 01T Target connector This target conne...

Page 510: ...integrating window function that associates the source program disassemble display and memory display with the trace result It should be used in combination with the device file sold separately ID78K...

Page 511: ...de control register 50 TMC50 183 8 bit timer mode control register 51 TMC51 183 A Asynchronous serial interface operation mode register 6 ASIM6 227 Asynchronous serial interface reception error status...

Page 512: ...Port mode register 1 PM1 76 Port mode register 12 PM12 76 Port mode register 3 PM3 76 Port mode register 6 PM6 76 Port register 0 P0 77 Port register 1 P1 77 Port register 12 P12 77 Port register 3 P3...

Page 513: ...F0CIE0 to UF0CIE255 346 UF0 data end register UF0DEND 313 UF0 descriptor length register UF0DSCL 344 UF0 device descriptor registers 0 to 17 UF0DD0 to UF0DD17 345 UF0 device status register L UF0DSTL...

Page 514: ...UF0IS0 294 UF0 INT status 1 register UF0IS1 296 UF0 INT status 2 register UF0IS2 298 UF0 INT status 3 register UF0IS3 299 UF0 INT status 4 register UF0IS4 300 UF0 interface 0 register UF0IF0 342 UF0...

Page 515: ...trol register 00 120 CSIC10 Serial clock selection register 10 258 CSIM10 Serial operation mode register 10 257 E EGN External interrupt falling edge enable register 400 EGP External interrupt rising...

Page 516: ...gister 00 123 PU0 Pull up resistor option register 0 78 PU1 Pull up resistor option register 1 78 PU12 Pull up resistor option register 12 78 PU3 Pull up resistor option register 3 78 PU6 Pull up resi...

Page 517: ...ce status register L 336 UF0E0L UF0 EP0 length register 323 UF0E0N UF0 EP0NAK register 282 UF0E0NA UF0 EP0NAKALL register 284 UF0E0R UF0 EP0 read register 322 UF0E0SL UF0 EP0 status register L 337 UF0...

Page 518: ...INT status 0 register 294 UF0IS1 UF0 INT status 1 register 296 UF0IS2 UF0 INT status 2 register 298 UF0IS3 UF0 INT status 3 register 299 UF0IS4 UF0 INT status 4 register 300 UF0MODC UF0 mode control...

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