CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U19014EJ1V0UD
82
(3) USB clock
•
PLL
This circuit multiplies the clock generated by the X1 oscillator (f
X
) or external main system clock (f
EXCLK
) by 8
or 12.
Multiplication ratio x8 or x12 can be selected using the PLLM bit of the PLL control register (PLLC), and
operation of PLL is started or stopped by setting the PLLSTOP bit.
Remarks 1.
f
X
:
X1 clock oscillation frequency
2.
f
EXCLK
:
external main system clock frequency
5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item Configuration
Control registers
Clock operation mode select register (OSCCTL)
Processor clock control register (PCC)
Internal oscillation mode register (RCM)
Main OSC control register (MOC)
Main clock mode register (MCM)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
PLL control register (PLLC)
USB clock control register (UCKC)
Oscillators
X1 oscillator
Internal high-speed oscillator
Internal low-speed oscillator
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