CHAPTER 12 USB FUNCTION CONTROLLER (USBF)
Preliminary User’s Manual U19014EJ1V0UD
322
12.4.2 Data hold registers
(1) UF0 EP0 read register (UF0E0R)
The UF0E0R register is a 64-byte FIFO that stores the OUT data sent from the host in the data stage of control
transfer to/from Endpoint0.
This register is read-only, in 8-bit units. A write access to this register is ignored.
The hardware automatically transfers data to the UF0E0R register when it has received the data from the host.
When the data has been correctly received, the E0ODT bit of the UF0IS1 register is set to 1. The UF0E0L
register holds the quantity of the received data, and an interrupt request (INTUSB0B) is issued. The UF0E0L
register always updates the length of the received data while it is receiving data. If the final transfer is correct
reception, the interrupt request is generated. If the reception is abnormal, the UF0E0L register is cleared to 0
and the interrupt request is not generated.
The data held by the UF0E0R register must be read by FW up to the value of the amount of data read by the
UF0E0L register. Check that all data has been read by using the EP0R bit of the UF0EPS0 register (EP0R = 0
when all data has been read). If the value of the UF0E0L register is 0, the EP0NKR bit of the UF0E0N register
is cleared to 0, and the UF0E0R register is ready for reception. The UF0E0R register is cleared when the next
SETUP token has been received.
Caution Read all the data stored. Clear the FIFO to discard some data.
E0R7
UF0E0R
E0R6
5
E0R5
E0R4
3
E0R3
2
E0R2
1
E0R1
E0R0
Address
FF02H
After reset
Undefined
0
4
6
7
Bit position
Bit name
Function
7 to 0
E0R7 to
E0R0
These bits store the OUT data sent from the host in the data stage of control transfer
to/from Endpoint0.
The operation of the UF0E0R register is illustrated below.
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