CHAPTER 18 OPTION BYTE
Preliminary User’s Manual U19014EJ1V0UD
448
18.2
Format of Option Byte
The format of the option byte is shown below.
Figure 18-1. Format of Option Byte (1/2)
Address: 0080H/1080H
Note
7 6 5 4 3 2 1 0
0 WINDOW1
WINDOW0
WDTON WDCS2 WDCS1 WDCS0 LSROSC
WINDOW1
WINDOW0
Watchdog timer window open period
0 0
0 1
1 0
Setting prohibited
1 1
100%
WDTON
Operation control of watchdog timer counter/illegal access detection
0
Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
1
Counter operation enabled (counting started after reset), illegal access detection operation enabled
WDCS2 WDCS1 WDCS0
Watchdog timer overflow time
0 0 0
2
10
/f
RL
(3.88 ms)
0 0 1
2
11
/f
RL
(7.76 ms)
0 1 0
2
12
/f
RL
(15.52 ms)
0 1 1
2
13
/f
RL
(31.03 ms)
1 0 0
2
14
/f
RL
(62.06 ms)
1 0 1
2
15
/f
RL
(124.12 ms)
1 1 0
2
16
/f
RL
(248.24 ms)
1 1 1
2
17
/f
RL
(496.48 ms)
LSROSC
Internal low-speed oscillator operation
0
Can be stopped by software (stopped when 1 is written to bit 0 (LSRSTOP) of RCM register)
1
Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
Note
Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
boot swap operation.
Cautions 1. The watchdog timer does not stop during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time taking this delay into consideration.
2. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
3. Be sure to clear bit 7 to 0.
Remarks 1.
f
RL
: Internal low-speed oscillation clock frequency
2.
( ): f
RL
= 264 kHz (MAX.)
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