CHAPTER 12 USB FUNCTION CONTROLLER (USBF)
Preliminary User’s Manual U19014EJ1V0UD
282
12.4 Register Configuration
12.4.1 Control registers
(1) UF0 EP0NAK register (UF0E0N)
This register controls NAK of Endpoint0 (except an automatically executed request).
This register can be read or written in 8-bit units (however, bit 0 can only be read).
It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have
been set. If it is necessary to read the status correctly, therefore, separate a write signal that accesses the
UF0FIC0 and UF0FIC1 registers from a read signal that accesses the UF0EPS0, UF0EPS1, UF0EPS2,
UF0E0N, and UF0EN registers by at least four USB clocks.
While NAK is being transmitted to Endpoint0 Read and Endpoint2, a write access to the EP0NKR bit is ignored.
0
UF0E0N
0
5
0
0
3
0
2
0
1
EP0NKR EP0NKW
Address
FF60H
After reset
00H
0
4
6
7
Bit position
Bit name
Function
1
EP0NKR
This bit controls NAK to the OUT token to Endpoint0 (except an automatically executed
request). It is automatically set to 1 by hardware when Endpoint0 has correctly received
data. It is also cleared to 0 by hardware when the data of the UF0E0R register has been
read by FW (counter value = 0).
1: Transmit NAK.
0: Do not transmit NAK (default value).
Set this bit to 1 by FW when data should not be received from the USB bus for some
reason even when USBF is ready for receiving data. In this case, USBF continues
transmitting NAK until this bit is cleared to 0 by FW. This bit is also cleared to 0 as soon
as the UF0E0R register has been cleared.
0
EP0NKW
This bit indicates how NAK to the IN token to Endpoint0 is controlled (except an
automatically executed request). This bit is automatically cleared to 0 by hardware when
the data of Endpoint0 is transmitted and the host correctly receives the transmitted data.
The data of the UF0E0W register is retained until this bit is cleared. Therefore, it is not
necessary to rewrite this bit even in the case of a retransmission request that is made if
the host could not receive data correctly. To send a short packet, be sure to set the
E0DED bit of the UF0DEND register to 1. This bit is automatically set to 1 when the
FIFO is full. As soon as the E0DED bit of the UF0DEND register is set to 1, the
EP0NKW bit is automatically set to 1 at the same time.
1: Do not transmit NAK.
0: Transmit NAK (default value).
If control transfer enters the status stage while ACK cannot be correctly received in the
data stage, this bit is cleared to 0 as soon as the UF0E0W register is cleared. This bit is
also cleared to 0 when UF0E0W is cleared by FW.
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