CHAPTER
5 C
L
OC
K
GENERA
TOR
Preliminary
User’s Manual
U19014EJ
1
V0UD
83
Figure 5-1. Block Diagram of Clock Generator
LSRSTOP
RSTS
RSTOP
PLLSTOP
PLLM
f
RL
CSS PCC2 PCC1 PCC0
f
XP
OSTS1 OSTS0
OSTS2
3
MOST
16
MOST
15
MOST
14
MOST
13
MOST
11
MCM0
XSEL
MCS
MSTOP
STOP
EXCLK OSCSEL
AMPH
4
f
XP
2
f
XP
2
2
f
XP
2
3
f
XP
2
4
f
RH
X1/P121
X2/EXCLK
/P122
f
XH
f
X
f
EXCLK
UCKCNT
PLL
f
XH
/2
USB clock
switch
f
USB
f
XH
/4
XSEL
X1 oscillation
stabilization time counter
Oscillation stabilization
time select register (OSTS)
Oscillation
stabilization
time counter
status register
(OSTC)
Internal bus
Internal bus
Main system
clock switch
Peripheral
hardware
clock switch
Controller
Main clock mode
register (MCM)
Peripheral
hardware
clock (f
PRS
)
CPU clock
(f
CPU
)
Processor clock control
register (PCC)
Prescaler
Selector
USB clock
(f
USB
)
Option byte
1: Cannot be stopped
0: Can be stopped
Internal low-
speed oscillator
(240 kHz (TYP.))
Watchdog timer,
8-bit timer H1
Prescaler
Internal oscillation
mode register
(RCM)
Internal high-
speed oscillator
(16 MHz (TYP.))
PLL control
register (RCM)
USB clock control
register (UCKC)
Clock operation mode
select register
(OSCCTL)
Main clock
mode register
(MCM)
Main OSC
control register
(MOC)
High-speed system
clock oscillator
Crystal/ceramic
oscillation
External input
clock
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