CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U19014EJ1V0UD
136
(2) Operation in clear & start mode entered by TI000 pin valid edge input
(CR000: compare register, CR010: capture register)
Figure 6-24. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Capture Register)
Timer counter
(TM00)
Clear
Output
controller
Edge
detector
Capture register
(CR010)
Capture signal
TO00 pin
Match signal
Interrupt signal
(INTTM000)
Interrupt signal
(INTTM010)
TI000 pin
Compare register
(CR000)
Operable bits
TMC003, TMC002
Count clock
Figure 6-25. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Capture Register) (1/2)
(a) TOC00 = 13H, PRM00 = 10H, CRC00, = 04H, TMC00 = 08H, CR000 = 0001H
TM00 register
0000H
Operable bits
(TMC003, TMC002)
Capture & count clear input
(TI000 pin input)
Compare register
(CR000)
Compare match interrupt
(INTTM000)
Capture register
(CR010)
Capture interrupt
(INTTM010)
TO00 pin output
0001H
10
Q
P
N
M
S
00
0000H
M
N
S
P
Q
This is an application example where the output level of the TO00 pin is inverted when the count value has been
captured & cleared.
The count value is captured to CR010 and TM00 is cleared (to 0000H) when the valid edge of the TI000 pin is
detected. When the count value of TM00 is 0001H, a compare match interrupt signal (INTTM000) is generated,
and the output level of the TO00 pin is inverted.
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