NEC mPD78F0730, Preliminary User'S Manual

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CHAPTER 12 USB FUNCTION CONTROLLER (USBF)
Preliminary User’s Manual U19014EJ1V0UD
311
(26) UF0 FIFO clear 0 register (UF0FIC0)
This register clears each FIFO.
This register is write-only, in 8-bit units. If this register is read, 00H is read.
FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been
written is automatically cleared to 0. Writing 0 to the bit is invalid.
The related bits are invalid if each endpoint is not supported by the setting of the UF0E1IM register and the
current setting of the interface.
0 UF0FIC0 0
5
BKI1SC BKI1CC
3
0
2
0
1
EP0WC EP0RC
Address
FF79H
After reset
00H
0 4 6 7
Bit position Bit name Function
5 BKI1SC This bit clears only the FIFO on the SIE side of the UF0BI1 register (reset the counter).
1: Clear
Writing this bit is invalid while an IN token for Endpoint 1 is being processed with the
BKI1NK bit set to 1.
The BKI1NK bit is automatically cleared to 0 by clearing the FIFO. Make sure that the
FIFO on the CPU side is empty when this bit is used.
4 BKI1CC This bit clears only the FIFO on the CPU side of the UF0BI1 register (reset the counter).
1: Clear
1 EP0WC This bit clears the UF0E0W register (resets the counter).
1: Clear
Writing to this bit is invalid while an IN token for Endpoint 0 is being processed with the
EP0NKW bit set to 1.
The EP0NKW bit is automatically cleared to 0 by clearing the FIFO.
0 EP0RC This bit clears the UF0E0R register (resets the counter).
1: Clear
When the EP0NKR bit is set to 1 (except when it has been set by FW), the EP0NKR bit
is automatically cleared to 0 by clearing the FIFO.
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