NEC mPD78F0730, Preliminary User'S Manual

Page: 137 / 518

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U19014EJ1V0UD
137
Figure 6-25. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Capture Register) (2/2)
(b) TOC00 = 13H, PRM00 = 10H, CRC00, = 04H, TMC00 = 0AH, CR000 = 0003H
TM00 register
0000H
Operable bits
(TMC003, TMC002)
Capture & count clear input
(TI000 pin input)
Compare register
(CR000)
Compare match interrupt
(INTTM000)
Capture register
(CR010)
Capture interrupt
(INTTM010)
TO00 pin output
0003H
0003H
10
Q P N M
S
00
0000H M
4 4 4 4
N S P Q
This is an application example where the width set to CR000 (4 clocks in this example) is to be output from the
TO00 pin when the count value has been captured & cleared.
The count value is captured to CR010, a capture interrupt signal (INTTM010) is generated, TM00 is cleared (to
0000H), and the output level of the TO00 pin is inverted when the valid edge of the TI000 pin is detected. When
the count value of TM00 is 0003H (four clocks have been counted), a compare match interrupt signal (INTTM000)
is generated and the output level of the TO00 pin is inverted.
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