CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Preliminary User’s Manual U19014EJ1V0UD
186
7.4 Operations of 8-Bit Timer/Event Counters 50 and 51
7.4.1 Operation as interval timer
8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals
of the count value preset to 8-bit timer compare register 5n (CR5n).
When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the
TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n
(TCL5n).
Setting
<1> Set the registers.
•
TCL5n:
Select the count clock.
•
CR5n:
Compare
value
•
TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n
and
CR5n.
(TMC5n = 0000
×××
0B
×
= Don’t care)
<2> After TCE5n = 1 is set, the count operation starts.
<3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> INTTM5n is generated repeatedly at the same interval.
Set TCE5n to 0 to stop the count operation.
Caution Do not write other values to CR5n during operation.
Remarks 1.
For how to enable the INTTM5n signal interrupt, see
CHAPTER 13 INTERRUPT FUNCTIONS
.
2.
n = 0, 1
Figure 7-11. Interval Timer Operation Timing (1/2)
(a) Basic operation
t
Count clock
TM5n count value
CR5n
TCE5n
INTTM5n
Count start
Clear
Clear
00H
01H
N
00H
01H
N
00H
01H
N
N
N
N
N
Interrupt acknowledged
Interrupt acknowledged
Interval time
Interval time
Remark
Interval time = (N + 1)
×
t
N = 01H to FFH
n = 0, 1
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