CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U19014EJ1V0UD
105
5.6.4 Example of controlling USB clock
The clock of the USB macro (f
USB
= 48 Mhz) uses multiplication of division clock of high-speed system clock ( f
XH)
by PLL.
●
Example of setting procedure when supplying the USB clock from the high-speed system clock (f
XH
= 12/16
MHz)
<1> Setting PLLSTOP to 1 (PLLC register)
When PLLSTOP is set to 1, the PLL stops operation.
<2> Setting PLLM to 0/1 (PLLC register)
In the case of f
XH
= 12 MHz, PLLM is set to 0 in order to select “8 times”.
In the case of f
XH
= 16 MHz, PLLM is set to 1 in order to select “12 times”.
<3> Setting XSEL to 1 (MCM register)
When XSEL is set to 1, the high-speed system clock is supplied to the PLL.
<4> Clearing PLLSTOP to 0 (PLLC register)
When PLLSTOP is cleared to 0, the PLL starts operating.
<5> Waiting for oscillation stabilization of the PLL
Wait for 800
µ
s by software. Other software processing can be executed while waiting.
<6> Setting UCKCNT to 1 (UCKC register)
When UCKCNT is set to 1, the USB clock is supplied to the USB macro.
[Control flow]
When f
XH
= 12 MHz, setting PLLM to 0.
When f
XH
= 16 MHz, setting PLLM to 1.
Setting XSEL to 1
PLL operation start (PLLSTOP = 0)
Oscillation stabilization wait (
800
µ
s)
USB clock supplying (UCKCNT = 1)
PLL operation stop (PLLSTOP = 1)
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