LRS Micro-g LaCoste FG5, Manual, Page: 82 / 149

Adjustment and Maintenance
4
also controls the state-machine clock source, clearing the state-machine counter,
and clearing the shaft encoder.
A second EPROM holds a programmable comparator level used for the setting of
trigger and hold points within the dropping chamber. One bit of the second
EPROM is also used to control the time-out circuitry (a safe-guard that protects
the motor and the test apparatus).
Eight bits address the two EPROM’s, giving a total of 256 programmable states.
One bit is reserved for a fail/standby state, reducing the system to 128 non-
standby states. These remaining states are subdivided into modes defined using
three bits of latched data (a total possibility of eight modes). Each mode can
have an associated four-bit state-machine cycle (sixteen possible states). A
counter which can be clocked by an external signal (the computer), by a window
comparator level, or by a programmable reference level in the dropping chamber
controls the latter four bits. These clock choices are stored in the first EPROM.
This architecture allows flexibility to program many different modes of
operation. Each mode can be associated with a programmable cyclic state-
machine. The circuitry also allows programmable digital set points for critical
positions such as launch points or hold points. The set points are well-controlled
against environmental variables.
The controller circuit board currently supports four different modes of
operation: STANDBY, MANUAL, OSCILLATE and DROP.
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