FAULTS
8-18
•
The fault record is copied into the area allocated for it in the new stack frame, beginning at
NFP-1. (See
Figure 8-4
.)
•
The processor gets the IP for the first instruction of the fault handling procedure from the
system procedure table (using the index provided in the fault table entry).
•
The processor stores the fault return code (001
2
) in the PFP register return type field. If the
fault is not a trace, parallel or override fault, it copies the state of the system procedure table
trace control flag (byte 12, bit 0) into the PC register trace enable bit. If the fault is a trace,
parallel or override fault, the trace enable bit is cleared.
On a return from the fault handling procedure, the processor performs the action described in
section 7.1.3.2, “Return Operation” (pg. 7-7)
with the addition of the following:
•
The fault record arithmetic controls field is copied into the AC register.
•
If the processor is in supervisor mode prior to the return from the fault handling procedure
(which it should be), the fault record process controls field is copied into the PC register. The
mode is then switched back to user, if it was in user mode before the call.
•
The processor switches back to the stack it was using when the fault occurred. (If the
processor was in user mode when the fault occurred, this operation causes a switch from the
supervisor stack to the user stack.)
•
If the trace-fault-pending flag and trace enable bits are set in the PC field of the fault record,
the trace fault on the instruction at the origin of the supervisor fault call is handled at this time.
The user should note that PC register restoration causes any changes to the process controls done
by the fault handling procedure to be lost.
8.8.4
Faults and Interrupts
If an interrupt occurs during an instruction that will fault, an instruction that has already faulted, or
fault handling procedure selection, the processor handles the interrupt in the following way:
1.
Completes the selection of the fault handling procedure.
2.
Creates the fault record.
3.
Services the interrupt just prior to executing the first instruction of the fault handling
procedure.
4.
Handles the fault upon return from the interrupt.
Handling the interrupt before the fault reduces interrupt latency.
Summary of Contents for i960 Jx
Page 1: ...Release Date December 1997 Order Number 272483 002 i960 Jx Microprocessor Developer s Manual ...
Page 24: ......
Page 25: ...1 INTRODUCTION ...
Page 26: ......
Page 35: ...2 DATA TYPES AND MEMORY ADDRESSING MODES ...
Page 36: ......
Page 46: ......
Page 47: ...3 PROGRAMMING ENVIRONMENT ...
Page 48: ......
Page 73: ...4 CACHE AND ON CHIP DATA RAM ...
Page 74: ......
Page 85: ...5 INSTRUCTION SET OVERVIEW ...
Page 86: ......
Page 111: ...6 INSTRUCTION SET REFERENCE ...
Page 112: ......
Page 233: ...7 PROCEDURE CALLS ...
Page 234: ......
Page 256: ......
Page 257: ...8 FAULTS ...
Page 258: ......
Page 291: ...9 TRACING AND DEBUGGING ...
Page 292: ......
Page 309: ...10 TIMERS ...
Page 310: ......
Page 324: ......
Page 325: ...11 INTERRUPTS ...
Page 326: ......
Page 369: ...12 INITIALIZATION AND SYSTEM REQUIREMENTS ...
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Page 412: ......
Page 413: ...13 MEMORY CONFIGURATION ...
Page 414: ......
Page 429: ...14 EXTERNAL BUS ...
Page 430: ......
Page 468: ......
Page 469: ...15 TEST FEATURES ...
Page 470: ......
Page 493: ...A CONSIDERATIONS FOR WRITING PORTABLE CODE ...
Page 494: ......
Page 502: ......
Page 503: ...B OPCODES AND EXECUTION TIMES ...
Page 504: ......
Page 515: ...C MACHINE LEVEL INSTRUCTION FORMATS ...
Page 516: ......
Page 523: ...D REGISTER AND DATA STRUCTURES ...
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Page 550: ......
Page 551: ...GLOSSARY ...
Page 552: ......
Page 561: ...INDEX ...
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