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EXTERNAL BUS

14-11

14

Figure 14-3

also shows a typical timing diagram for a non-burst, 32-bit write transaction. For the

write operation, W/R and DT/R are high to denote the direction of the data flow. The D/C pin is
high since instruction code cannot be written. During the Tw/Td state, the processor drives data on
the bus, waiting to sample RDYRCV low to terminate the transfer. The figure shows RDYRCV
assertion by external logic, so this state is a data state and the processor enters the recovery state.

At the end of a write, notice that the write data is driven during Tr and any subsequent Ti states.
After a write, the processor will drive write data until the next Ta state. See

section 14.2.4, “Bus

and Control Signals During Recovery and Idle States” (pg. 14-22)

for details.

14.2.3.3

Burst Transactions

A burst access is an address cycle followed by two to four data transfers. The i960 Jx micropro-
cessor uses burst transactions for instruction fetching and accessing system data structures.
Therefore, a system design incorporating an i960 Jx microprocessor must support burst transac-
tions. Burst accesses can also result from instruction references to data types which exceed the
width of the bus.

Maximum burst size is four data transfers, independent of bus width. A byte-wide bus has a
maximum burst size of four bytes; a word-wide bus has a maximum of four words. For an 8- or
16-bit bus, this means that some bus requests may result in multiple burst accesses. For example, if
a quad word load request (e.g., ldq instruction) is made to an 8-bit data region, it results in four,
4-byte, burst accesses. (See

Table 14-6 (pg. 14-23)

.

Burst accesses on a 32-bit bus are always aligned to even-word boundaries. Quad-word and
triple-word accesses always begin on quad-word boundaries (A3:2=00); double-word transfers
always begin on double-word boundaries (A2=0); single-word transfers occur on single word
boundaries.

Figure 14-4

shows burst, stop and start addresses for a 32-bit bus.

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Summary of Contents for i960 Jx

Page 1: ...Release Date December 1997 Order Number 272483 002 i960 Jx Microprocessor Developer s Manual ...

Page 2: ...thout notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The i960 Jx Processor may contain design defects or errors known as errata which may cause the product to devi...

Page 3: ... 8 1 3 1 Reserved and Preserved 1 8 1 3 2 Specifying Bit and Signal Values 1 9 1 3 3 Representing Numbers 1 9 1 3 4 Register Names 1 9 1 4 Related Documents 1 10 CHAPTER 2 DATA TYPES AND MEMORY ADDRESSING MODES 2 1 DATA TYPES 2 1 2 1 1 Integers 2 2 2 1 2 Ordinals 2 2 2 1 3 Bits and Bit Fields 2 3 2 1 4 Triple and Quad Words 2 3 2 1 5 Register Data Alignment 2 3 2 1 6 Literals 2 4 2 2 BIT AND BYTE ...

Page 4: ...ction Cache 3 16 3 5 6 Data Cache 3 17 3 6 LOCAL REGISTER CACHE 3 17 3 7 PROCESSOR STATE REGISTERS 3 17 3 7 1 Instruction Pointer IP Register 3 17 3 7 2 Arithmetic Controls AC Register 3 18 3 7 2 1 Initializing and Modifying the AC Register 3 18 3 7 2 2 Condition Code AC cc 3 19 3 7 3 Process Controls PC Register 3 21 3 7 3 1 Initializing and Modifying the PC Register 3 22 3 7 4 Trace Controls TC ...

Page 5: ...ovement 5 5 5 2 1 1 Load and Store Instructions 5 5 5 2 1 2 Move 5 6 5 2 1 3 Load Address 5 6 5 2 2 Select Conditional 5 6 5 2 3 Arithmetic 5 7 5 2 3 1 Add Subtract Multiply Divide Conditional Add Conditional Subtract 5 8 5 2 3 2 Remainder and Modulo 5 8 5 2 3 3 Shift Rotate and Extended Shift 5 9 5 2 3 4 Extended Arithmetic 5 10 5 2 4 Logical 5 10 5 2 5 Bit Bit Field and Byte Operations 5 11 5 2 ...

Page 6: ...R3 As Destinations for MDU Instructions 5 23 5 3 2 3 Use Global Registers g0 g14 As Destinations for MDU Instructions 5 23 5 3 2 4 Execute in Imprecise Fault Mode 5 24 CHAPTER 6 INSTRUCTION SET REFERENCE 6 1 NOTATION 6 1 6 1 1 Alphabetic Reference 6 2 6 1 2 Mnemonic 6 2 6 1 3 Format 6 2 6 1 4 Description 6 3 6 1 5 Action 6 3 6 1 6 Faults 6 5 6 1 7 Example 6 5 6 1 8 Opcode and Instruction Format 6 ...

Page 7: ... FAULT cc 6 52 6 2 30 flushreg 6 54 6 2 31 fmark 6 55 6 2 32 halt 6 56 6 2 33 icctl 6 58 6 2 34 intctl 6 66 6 2 35 intdis 6 68 6 2 36 inten 6 69 6 2 37 LOAD 6 70 6 2 38 lda 6 73 6 2 39 mark 6 74 6 2 40 modac 6 75 6 2 41 modi 6 76 6 2 42 modify 6 77 6 2 43 modpc 6 78 6 2 44 modtc 6 80 6 2 45 MOVE 6 81 6 2 46 muli mulo 6 84 6 2 47 nand 6 85 6 2 48 nor 6 86 6 2 49 not notand 6 87 6 2 50 notbit 6 88 6...

Page 8: ... 2 5 Previous Frame Pointer 7 5 7 1 2 6 Return Type Field 7 5 7 1 2 7 Return Instruction Pointer 7 5 7 1 3 Call and Return Action 7 5 7 1 3 1 Call Operation 7 6 7 1 3 2 Return Operation 7 7 7 1 4 Caching Local Register Sets 7 7 7 1 4 1 Reserving Local Register Sets for High Priority Interrupts 7 8 7 1 5 Mapping Local Registers to the Procedure Stack 7 11 7 2 MODIFYING THE PFP REGISTER 7 11 7 3 PAR...

Page 9: ...dling Procedure Actions 8 13 8 7 2 Program Resumption Following a Fault 8 13 8 7 2 1 Faults Happening Before Instruction Execution 8 13 8 7 2 2 Faults Happening During Instruction Execution 8 14 8 7 2 3 Faults Happening After Instruction Execution 8 14 8 7 3 Return Instruction Pointer RIP 8 14 8 7 4 Returning to the Point in the Program Where the Fault Occurred 8 15 8 7 5 Returning to a Point in t...

Page 10: ...egister 9 7 9 2 7 5 Data Address Breakpoint DAB Registers 9 9 9 2 7 6 Instruction Breakpoint IPB Registers 9 10 9 3 GENERATING A TRACE FAULT 9 11 9 4 HANDLING MULTIPLE TRACE EVENTS 9 11 9 5 TRACE FAULT HANDLING PROCEDURE 9 12 9 5 1 Tracing and Interrupt Procedures 9 12 9 5 2 Tracing on Calls and Returns 9 12 9 5 2 1 Tracing on Explicit Call 9 13 9 5 2 2 Tracing on Implicit Call 9 14 9 5 2 3 Tracin...

Page 11: ... 5 INTERRUPT STACK AND INTERRUPT RECORD 11 7 11 6 MANAGING INTERRUPT REQUESTS 11 8 11 6 1 External Interrupts 11 8 11 6 2 Non Maskable Interrupt NMI 11 8 11 6 3 Timer Interrupts 11 9 11 6 4 Software Interrupts 11 9 11 6 5 Posting Interrupts 11 9 11 6 5 1 Posting Software Interrupts via sysctl 11 9 11 6 5 2 Posting Software Interrupts Directly in the Interrupt Table 11 11 11 6 5 3 Posting External ...

Page 12: ...11 37 11 9 4 Maximum Interrupt Latency 11 38 11 9 4 1 Avoiding Certain Destinations for MDU Operations 11 42 11 9 4 2 Masking Integer Overflow Faults for syncf 11 42 CHAPTER 12 INITIALIZATION AND SYSTEM REQUIREMENTS 12 1 OVERVIEW 12 1 12 2 INITIALIZATION 12 2 12 2 1 Reset State Operation 12 3 12 2 2 Self Test Function STEST FAIL 12 6 12 2 2 1 The STEST Pin 12 7 12 2 2 2 External Bus Confidence Tes...

Page 13: ... 3 1 Bus Width 13 5 13 4 Physical Memory Attributes at Initialization 13 5 13 4 1 Bus Control BCON Register 13 6 13 5 Boundary Conditions for Physical Memory Regions 13 7 13 5 1 Internal Memory Locations 13 7 13 5 2 Bus Transactions Across Region Boundaries 13 7 13 5 3 Modifying the PMCON Registers 13 7 13 6 Programming the Logical Memory Attributes 13 8 13 6 1 Defining the Effective Range of a Lo...

Page 14: ... 14 33 14 3 BUS APPLICATIONS 14 34 14 3 1 System Block Diagrams 14 34 14 3 1 1 Memory Subsystems 14 37 14 3 1 2 I O Subsystems 14 37 CHAPTER 15 TEST FEATURES 15 1 ON CIRCUIT EMULATION ONCE 15 1 15 1 1 Entering Exiting ONCE Mode 15 1 15 2 BOUNDARY SCAN JTAG 15 2 15 2 1 Boundary Scan Architecture 15 2 15 2 1 1 TAP Controller 15 2 15 2 1 2 Instruction Register 15 2 15 2 1 3 Test Data Registers 15 2 1...

Page 15: ...NSIDERATIONS FOR WRITING PORTABLE CODE A 1 CORE ARCHITECTURE A 1 A 2 ADDRESS SPACE RESTRICTIONS A 2 A 2 1 Reserved Memory A 2 A 2 2 Initialization Boot Record A 2 A 2 3 Internal Data RAM A 2 A 2 4 Instruction Cache A 2 A 3 Data and Data Structure Alignment A 3 A 4 RESERVED LOCATIONS IN REGISTERS AND DATA STRUCTURES A 4 A 5 INSTRUCTION SET A 4 A 5 1 Instruction Timing A 4 A 5 2 Implementation Speci...

Page 16: ...C 1 GENERAL INSTRUCTION FORMAT C 1 C 2 REG FORMAT C 2 C 3 COBR FORMAT C 3 C 4 CTRL FORMAT C 4 C 5 MEM FORMAT C 4 C 5 1 MEMA Format Addressing C 5 C 5 2 MEMB Format Addressing C 6 APPENDIX D REGISTER AND DATA STRUCTURES D 1 REGISTERS D 3 GLOSSARY INDEX ...

Page 17: ... Breakpoint Resource Request 6 115 Figure 7 1 Procedure Stack Structure and Local Registers 7 3 Figure 7 2 Frame Spill 7 9 Figure 7 3 Frame Fill 7 10 Figure 7 4 System Procedure Table 7 16 Figure 7 5 Previous Frame Pointer Register PFP r0 7 20 Figure 8 1 Fault Handling Data Structures 8 1 Figure 8 2 Fault Table and Fault Table Entries 8 5 Figure 8 3 Fault Record 8 7 Figure 8 4 Storage of the Fault...

Page 18: ...es Termination 12 39 Figure 12 12 AC Termination 12 39 Figure 12 13 Avoid Closed Loop Signal Paths 12 41 Figure 13 1 PMCON and LMCON Example 13 2 Figure 13 2 PMCON Register Bit Description 13 5 Figure 13 3 Bus Control Register BCON 13 6 Figure 13 4 Logical Memory Template Starting Address Registers LMADR0 1 13 8 Figure 13 5 Logical Memory Template Mask Registers LMMR0 1 13 9 Figure 13 6 Default Lo...

Page 19: ...r 15 17 Figure 15 5 Timing diagram illustrating the loading of Data Register 15 18 Figure C 1 Instruction Formats C 1 Figure D 1 AC Arithmetic Controls Register D 3 Figure D 2 PC Process Controls Register D 4 Figure D 3 Procedure Stack Structure and Local Registers D 5 Figure D 4 System Procedure Table D 6 Figure D 5 PFP Previous Frame Pointer Register r0 D 7 Figure D 6 Fault Table and Fault Table...

Page 20: ...3 Figure D 25 PMCON Register Bit Description D 23 Figure D 26 BCON Bus Control Register D 24 Figure D 27 DLMCON Default Logical Memory Configuration Register D 24 Figure D 28 LMADR0 1 Logical Memory Template Starting Address Registers D 25 Figure D 29 LMMR0 1 Logical Memory Mask Registers D 25 ...

Page 21: ...ns 5 7 Table 6 1 Pseudo Code Symbol Definitions 6 4 Table 6 2 Faults Applicable to All Instructions 6 4 Table 6 3 Common Faulting Conditions 6 5 Table 6 4 Condition Code Mask Descriptions 6 7 Table 6 5 Condition Code Mask Descriptions 6 21 Table 6 6 Condition Code Settings 6 31 Table 6 7 Condition Code Settings 6 32 Table 6 8 Condition Code Settings 6 33 Table 6 9 Condition Code Mask Descriptions ...

Page 22: ... RAM 11 36 Table 11 3 Base Interrupt Latency 11 37 Table 11 4 Worst Case Interrupt Latency Controlled by divo to Destination r15 11 38 Table 11 5 Worst Case Interrupt Latency Controlled by divo to Destination r3 11 39 Table 11 6 Worst Case Interrupt Latency Controlled by calls 11 39 Table 11 7 Worst Case Interrupt Latency When Delivering a Software Interrupt 11 40 Table 11 8 Worst Case Interrupt L...

Page 23: ...odings B 2 Table B 3 COBR Format Instruction Encodings B 6 Table B 4 CTRL Format Instruction Encodings B 7 Table B 5 Cycle Counts for sysctl Operations B 7 Table B 6 Cycle Counts for icctl Operations B 8 Table B 7 Cycle Counts for dcctl Operations B 8 Table B 8 Cycle Counts for intctl Operations B 8 Table B 9 MEM Format Instruction Encodings B 9 Table B 10 Addressing Mode Performance B 10 Table C ...

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Page 25: ...1 INTRODUCTION ...

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Page 27: ...ontrol registers external bus Programmable Bus Control Unit 80960JF JD 4 Kbyte Two way Set Associative Interrupt Controller Control Address Instruction Sequencer Physical Region Configuration Interrupt Port 1 Kbyte Data RAM Instruction Cache Memory Interface Execution Multiply Unit Divide Unit Memory Mapped Register Interface Data Cache JF JD 2 Kbyte Direct Mapped Data Bus Global Local Register Fi...

Page 28: ...ect mapped data cache The i960 JF and JD processors feature a 2 Kbyte direct mapped data cache that is write through and write allocate i960 JA processors feature a 1 Kbyte direct mapped data cache These processors have a line size of four words and implement a natural fill policy Each line in the cache has a valid bit to reduce fetch latency on cache misses each word within a line also has a vali...

Page 29: ...ides a flexible low latency means for requesting interrupts It handles the posting of interrupts requested by hardware and software sources Acting indepen dently from the core the interrupt controller compares the priorities of posted interrupts with the current process priority off loading this task from the core The interrupt controller is compatible with i960 CA CF processors The interrupt cont...

Page 30: ...request to the i960 Jx processor interrupt controller See CHAPTER 10 TIMERS for a complete description 1 1 7 Memory Mapped Control Registers MMR Control registers in the i960 Jx processor are memory mapped to allow for visibility to application software This includes registers for memory configuration internally cached PRCB data breakpoint registers and interrupt control These registers are mapped...

Page 31: ...electrical specifications such as DC and AC parametrics operating conditions and packaging specifications Such information is found in the product s data sheets 80960JA JF Embedded 32 bit Microprocessor Data Sheet 272504 80960JD Embedded 32 bit Microprocessor Data Sheet 272596 80L960JA JF 3 3 V Embedded 32 bit Microprocessor Data Sheet 272744 80960JA JF 3 3 V Embedded 32 bit Microprocessor Data Sh...

Page 32: ...ntain unusual values A preserved field is one that the processor does not use Software may use preserved fields for any function Reserved fields in certain data structures should be cleared set to zero when the data structure is created Clear the reserved fields when creating the Interrupt Table Fault Table and System Procedure Table Software should not modify or rely on these reserved field value...

Page 33: ...that a number is a binary number the 2 subscript may be omitted Hexadecimal numbers are designated in text with the suffix H for example FFFF FF5AH In pseudo code action statements in the instruction reference section and occasionally in text hexadecimal numbers are represented by adding the C language convention 0x as a prefix For example FF7AH appears as 0xFF7A in the pseudo code 1 3 4 Register ...

Page 34: ...t your local sales representative for more information on obtaining Intel documents including Specification Updates 80960JA JF Embedded 32 bit Microprocessor Data Sheet 272504 80960JD Embedded 32 bit Microprocessor Data Sheet 272596 80L960JA JF 3 3 V Embedded 32 bit Microprocessor Data Sheet 272744 80960JA JF 3 3 V Embedded 32 bit Microprocessor Data Sheet 273146 80960JD 3 3 V Embedded 32 bit Micr...

Page 35: ...2 DATA TYPES AND MEMORY ADDRESSING MODES ...

Page 36: ......

Page 37: ...ong Word 64 bits Triple Word 96 bits Quad Word 128 bits Bit Field Bit Byte Short Word Triple Word Quad Word 8 Bits 16 Bits 32 Bits 64 Bits 96 Bits 128 Bits Numeric Integer Numeric Ordinal Non Numeric Byte Integer Short Integer Integer Byte Ordinal Short Ordinal Ordinal Bit Bit Field Triple Word Quad Word 8 Bits 16 Bits 32 Bits 8 Bits 16 Bits 32 Bits 1 Bit 1 32 Bits 96 Bits 128 Bits 27 to 27 1 215 ...

Page 38: ...e or short word the value is truncated and the integer overflow condition is signalled When an overflow occurs either an AC register flag is set or the ARITH METIC INTEGER_OVERFLOW fault is generated depending on the Integer Overflow Mask bit AC om in the AC register CHAPTER 8 FAULTS describes the integer overflow fault For instructions ld load word and st store word data is moved directly between...

Page 39: ...the bit number of its lowest numbered bit 0 31 Loading and storing bit and bit field data is normally performed using the ordinal load ldo and store sto instructions When an ldi instruction loads a bit or bit field value into a 32 bit register the processor appends sign extension bits A byte or short store can signal an integer overflow condition 2 1 4 Triple and Quad Words Triple and quad words r...

Page 40: ...nd size When a literal is used in an instruction that requires integer operands the processor treats the literal as a positive integer value 2 2 BIT AND BYTE ORDERING IN MEMORY All occurrences of numeric and non numeric data types except bits and bit fields must start on a byte boundary Any data item occupying multiple bytes is stored as big endian or little endian The following sections further d...

Page 41: ...bit 7 for bytes Byte ordering affects the way the i960 Jx processor handles bus accesses See section 13 6 2 Selecting the Byte Order pg 13 12 for more information Table 2 1 Memory Contents for Little and Big Endian Example ADDRESS DATA 1000H 12H 1001H 34H 1002H 56H 1003H 78H 1004H 9AH 1005H BCH 1006H DEH 1007H F0H Table 2 2 Byte Ordering for Little and Big Endian Accesses Access Example Register C...

Page 42: ...rger than 4095 exp MEMB Register Indirect abase reg MEMB with offset abase offset exp reg MEMA with displacement abase displacement exp reg MEMB with index abase index scale reg reg scale MEMB with index and displacement abase index scale displacement exp reg reg scale MEMB Index with displacement index scale displacement exp reg scale MEMB instruction pointer IP with displacement IP displacement ...

Page 43: ...ecified through arithmetic expressions e g x 44 or symbolic labels After evaluating an address specified with the absolute addressing mode the assembler converts the address into an offset or displacement and selects the appropriate instruction encoding format and addressing mode 2 3 2 Register Indirect Register indirect addressing modes use a register s 32 bit value as a base for address calculat...

Page 44: ...efore displacement is added This mode uses MEMB format 2 3 4 IP with Displacement This addressing mode is used with load and store instructions to make them instruction pointer IP relative IP with displacement addressing mode references the next instruction s address plus the displacement This mode uses MEMB format 2 3 5 Addressing Mode Examples The following examples show how i960 processor addre...

Page 45: ...d word beginning at memory location r8 r9 scaled by 4 loaded into r4 through r7 st g3 xyz g4 g5 2 Register indirect with index and displacement word in g3 stored to mem location g4 xyz g5 scaled by 2 ldis xyz r12 2 r13 Index with displacement load short integer at memory location xyz r12 into r13 and sign extended st r4 xyz ip ip with displacement store word in r4 at memory location IP xyz 8 array...

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Page 47: ...3 PROGRAMMING ENVIRONMENT ...

Page 48: ......

Page 49: ... uses load and store instruc tions to access memory All operations take place at the register level The processor uses 16 global registers 16 local registers and 32 literals constants 0 31 as instruction operands The global register numbers are g0 through g15 local register numbers are r0 through r15 Several of these registers are used for dedicated functions For example register r0 is the previou...

Page 50: ...heir contents across procedure boundaries They provide a fast and efficient means of passing parameters between procedures Architecturally Defined Data Structures FFFF FFFFH Instruction Stream Instruction Execution Processor State Registers Instruction Pointer Arithmetic Controls Process Controls Trace Controls Address Space Sixteen 32 Bit Global Registers Sixteen 32 Bit Local Registers g0 g15 r0 ...

Page 51: ...s a new set of local registers and saves the calling procedure s local registers When the application returns from the procedure the local registers are released for the next procedure call The processor performs local register management a program need not explicitly save and restore these registers Local registers r3 through r15 are general purpose registers r0 through r2 are reserved for specia...

Page 52: ...s Example 3 1 Register Scoreboarding 3 2 4 Literals The architecture defines a set of 32 literals that can be used as operands in many instructions These literals are ordinal unsigned values that range from 0 to 31 5 bits When a literal is used as an operand the processor expands it to 32 bits by adding leading zeros When the instruction requires an operand larger than 32 bits the processor zero e...

Page 53: ...2 shows an example of correct and incorrect register alignment Example 3 2 Register Alignment Global registers local registers and literals are used directly as instruction operands Table 3 2 lists instruction operands for each machine level instruction format and the positions that can be filled by each register or literal movl g3 g8 Incorrect alignment resulting value in registers g8 and g9 is u...

Page 54: ...s based on their addresses Addresses FF00 0000H through FF00 7FFFH are allocated to user space memory mapped registers Addresses FF00 8000H to FFFF FFFFH are allocated to supervisor space registers 3 3 1 1 Restrictions on Instructions that Access Memory Mapped Registers The majority of memory mapped registers can be accessed by both load ld and store st instruc tions However some registers have re...

Page 55: ...lt 2 When the access is a store in user mode to an implemented supervisor location a TYPE MISMATCH fault occurs It is unpredictable whether a store to an unimplemented supervisor location causes a fault 3 When the access is neither of the above the access is attempted Note that an MMR may generate faults based on conditions specific to that MMR Example trying to write the timer registers in user m...

Page 56: ...section 9 2 7 2 Hardware Breakpoints pg 9 5 for details about getting modification rights to breakpoint registers Sysctl RwG sysctl Read when Granted The value of the register can only be read by executing a sysctl instruction issued with the modify memory mapped register message type Modification rights to the register must be granted first or an OPERATION UNIMPLEMENTED fault occurs when the sysc...

Page 57: ... 0 FF00 8400H Sysctl RwG WwG IPB1 Instruction Address Breakpoint Register 1 FF00 8404H Sysctl RwG WwG Reserved FF00 8408H to FF00 841FH DAB0 Data Address Breakpoint Register 0 FF00 8420H R W WwG DAB1 Data Address Breakpoint Register 1 FF00 8424H R W WwG Reserved FF00 8428H to FF00 843FH BPCON Breakpoint Control Register FF00 8440H R W WwG Reserved FF00 8444H to FF00 84FFH IPND Interrupt Pending Re...

Page 58: ...al Memory Control Register 5 FF00 8628H R W Reserved FF00 862CH PMCON12_13 Physical Memory Control Register 6 FF00 8630H R W Reserved FF00 8634H PMCON14_15 Physical Memory Control Register 7 FF00 8638H R W Reserved FF00 863CH to FF00 86F8H BCON Bus Configuration Control Register FF00 86FCH R W PRCB Processor Control Block Pointer FF00 8700H RO ISP Interrupt Stack Pointer FF00 8704H R W SSP Supervi...

Page 59: ...able interrupt table interrupt stack fault table and control table are specified in the processor control block Supervisor stack location is specified in the system procedure table User stack location is specified in the user s startup code Of these structures only the system procedure table fault table control table and initialization data structures may be in ROM the interrupt table and stacks m...

Page 60: ...de to supervisor mode When the processor switches modes it also switches to the supervisor stack Interrupt Table section 11 4 INTERRUPT TABLE pg 11 4 The interrupt table contains vectors pointers to interrupt handling procedures When an interrupt is serviced a particular interrupt table entry is specified Fault Table section 8 3 FAULT TABLE pg 8 4 Contains pointers to fault handling procedures Whe...

Page 61: ...ddress space such as segments For memory management an external memory management unit MMU may subdivide memory into pages or restrict access to certain areas of memory to protect a kernel s code data and stack However the processor views this address space as linear 0000 0000H Address 0000 03FFH 0000 0400H FFFF FFFFH FEFF FF2FH FEFF FF30H FEFF FF60H FEFF FF5FH Reserved Memory Code data Architectu...

Page 62: ... external agent can read or write the same location The processor requires indivisible access within an aligned 16 byte block of memory atomic access A read modify write operation Here the external memory system must guarantee that once a processor begins a read modify write operation on an aligned 16 byte block of memory it is allowed to complete the operation before another processor or external...

Page 63: ...fter the access is completed the processor can generate an OPERATION UNALIGNED fault when directed to do so Unaligned fault handling is enabled at initialization based on the value of the Fault Configuration Word in the Process Control Block See section 12 3 1 2 Process Control Block PRCB pg 12 16 3 5 3 Byte Word and Bit Addressing The processor provides instructions for moving data blocks of vari...

Page 64: ...y higher numbered registers Individual bits can be addressed only in data that resides in a register bit 0 in a register is the least significant bit bit 31 is the most significant bit 3 5 4 Internal Data RAM Internal data RAM is mapped to the lower 1 Kbyte 0000H to 03FFH of the address space Loads and stores with target addresses in internal data RAM operate directly on the internal data RAM no e...

Page 65: ...ter The IP register contains the address of the instruction currently being executed This address is 32 bits long however since instructions are required to be aligned on word boundaries in memory the IP s two least significant bits are always 0 zero All i960 processor instructions are either one or two words long The IP gives the address of the lowest order byte of the first word of the instructi...

Page 66: ...image in the PRCB Software can use the modify arithmetic controls modac instruction to examine and or modify any of the register bits This instruction provides a mask operand that lets user software limit access to the register s specific bits or groups of bits such as the reserved bits The processor automatically saves and restores the AC register when it services an interrupt or handles a fault ...

Page 67: ...tions for the extended arithmetic instructions To show true or false conditions the processor sets the flags as shown in Table 3 8 To show equality and inequalities the processor sets the condition code flags as shown in Table 3 9 The term unordered is used when comparing floating point numbers The i960 Jx processor does not implement on chip floating point processing To show carry out and overflo...

Page 68: ...ault is masked and integer overflow is encountered the processor sets the integer overflow flag instead of generating a fault When the fault is not masked the fault is allowed to occur and the flag is not set Once the processor sets this flag the flag remains set until the application software clears it Refer to the discussion of the ARITHMETIC INTEGER_OVERFLOW fault in CHAPTER 8 FAULTS for more i...

Page 69: ...errupts When nested interrupts occur the processor remains in the interrupted state until all interrupts are handled then switches back to the executing state on the return from the initial interrupt procedure The PC register priority field bits 16 through 20 indicates the processor s current executing or interrupted priority The architecture defines a mechanism for prioritizing execution of code ...

Page 70: ...modpc in user mode with a non zero mask As with modac modpc provides a mask operand that can be used to limit access to specific bits or groups of bits in the register In user mode software can use modpc to read the current PC register In the latter two methods the interrupt or fault handler changes process controls in the interrupt or fault record that is saved on the stack Upon return from the i...

Page 71: ...or stack Switching to the supervisor stack helps maintain a kernel s integrity For example it allows access to system debugging software or a system monitor even when an application s program destroys its own stack In supervisor mode the processor is allowed access to a set of supervisor only functions and instructions For example the processor uses supervisor mode to handle interrupts and trace f...

Page 72: ...ns in that mode until a return is performed to the procedure that caused the original mode switch Interrupts and faults can cause the processor to switch from user to supervisor mode When the processor handles an interrupt it automatically switches to supervisor mode However it does not switch to the supervisor stack Instead it switches to the interrupt stack Fault table entries determine when a p...

Page 73: ...4 CACHE AND ON CHIP DATA RAM ...

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Page 75: ...nal data RAM is controlled by the byte endian control bit in the DLMCON register Some internal data RAM locations are reserved for functions other than general data storage The first 64 bytes of data RAM may be used to cache interrupt vectors which reduces latency for these interrupts The word at location 0000H is always reserved for the cached NMI vector With the exception of the cached NMI vecto...

Page 76: ...perations by using an internal local register cache also known as a stack frame cache Up to 7 local register sets can be contained in the cache before sets must be saved in external memory The register set is all the local registers i e r0 through r15 The processor uses a 128 bit wide bus to store local register sets quickly to the register cache An integrated procedure call mechanism saves the cu...

Page 77: ...of free frames within the register cache that can be used by high priority interrupts only Any attempt by non critical code to reduce the number of free frames below this value results in a frame flush to external memory The free frame check is performed only when a frame is pushed which occurs only for an implicit or explicit call The following pseudo code illustrates the operation of the registe...

Page 78: ...sm to disable the cache The cache is managed through the icctl or sysctl instruction Using icctl is the preferred and more versatile method for controlling the instruction cache on the i960 Jx processor Future i960 processors may not support sysctl instruction Cache misses cause the processor to issue a double word or a quad word fetch based on the location of the Instruction Pointer When the IP i...

Page 79: ...ock out all normal updates to this one way of the cache This cache load and lock mechanism is provided to minimize latency on program control transfers to key operations such as interrupt service routines The block size that can be loaded and locked on the i960 Jx processor is one way of the cache Any code can be locked into the cache not just interrupt routines An icctl or sysctl instruction is i...

Page 80: ...ithin a line also has a valid bit Caches are managed through the dcctl instruction User settings in the memory region configuration registers LMCON0 1 and DLMCON determine which data accesses are cacheable or non cacheable based on memory region 4 5 1 Enabling and Disabling the Data Cache To cache data two conditions must be met 1 The data cache must be enabled A dcctl instruction issued with an e...

Page 81: ... by a ldl ldt or ldq instruction miss the data cache every word accessed by that load instruction is updated in the cache In each case the external bus accesses used to acquire the data may consist of none one or several burst accesses based on the alignment of the data and the bus width of the memory region that contains the data See CHAPTER 14 EXTERNAL BUS for more details A multi word load acce...

Page 82: ...f a miss for a word or multi word store a tag and cache line are allocated when needed and the appropriate valid bits line and word s are updated 3 In the case of byte or short word data that hits a valid word in the cache both the word in cache and external memory are updated with the data the cache word remains valid 4 In the case of byte or short word data that falls within a valid line but mis...

Page 83: ... falls into an address range mapped by an enabled LMCON or DLMCON and the data caching enabled bit in the matching LMCON is clear 2 The entire data cache is disabled 3 The access is a read operation of the read modify write sequence performed by an atmod or atadd instruction 4 The access is an implicit read access to the interrupt table to post or deliver a software interrupt When the memory locat...

Page 84: ...e is to program the LMCON0 1 registers such that I O regions are non cacheable Partitioning the system in this fashion eliminates I O as a source of coherency problems See section 13 6 Programming the Logical Memory Attributes pg 13 8 for more information on this subject 4 5 7 Data Cache Visibility The data cache status can be determined by a dcctl instruction issued with a data cache status messa...

Page 85: ...5 INSTRUCTION SET OVERVIEW ...

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Page 87: ... For example the add ordinal instruction is referred to as addo The Intel 80960 assembly language syntax consists of the instruction mnemonic followed by zero to three operands separated by commas In the following assembly language statement ordinal operands in global registers g5 and g9 are added together and the result is stored in g7 addo g5 g9 g7 g7 g9 g5 In the assembly language listings in t...

Page 88: ...REG Most instructions are encoded in this format Used primarily for instructions which perform register to register operations compare and branch COBR An encoding optimization which combines compare and branch operations into one opword Other compare and branch operations are also provided as REG and CTRL format instructions control CTRL Used for branches and calls that do not depend on registers ...

Page 89: ...1 src2 displacement src1 src2 indicate values to be compared displacement indicates branch target src1 can specify a global register local register or a literal src2 can specify a global or local register MEM src dst efa Specifies source or destination register and an effective address efa formed by using the processor s addressing modes as described in section 2 3 MEMORY ADDRESSING MODES pg 2 6 R...

Page 90: ...nded Multiply Extended Divide Add with Carry Subtract with Carry Conditional Add Conditional Subtract Rotate And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit Extract Modify Scan Byte for Equal Byte Swap Comparison Branch Call Return Fault Compare Conditional Compare Compare and Increment Compare and Decremen...

Page 91: ...pies 8 bytes into 2 successive registers ldt copies 12 bytes into 3 successive registers ldq copies 16 bytes into 4 successive registers st copies 4 bytes from a register into memory stl copies 8 bytes from 2 successive registers stt copies 12 bytes from 3 successive registers stq copies 16 bytes from 4 successive registers For ld ldob ldos ldib and ldis the instruction specifies a memory address ...

Page 92: ...ve instructions copy data from a local or global register or group of registers to another register or group of registers These instructions use the REG format 5 2 1 3 Load Address The Load Address instruction lda computes an effective address in the address space from an operand presented in one of the addressing modes lda is commonly used to load a constant into a register This instruction uses ...

Page 93: ...ions which handle specific requirements for in place memory operations All arithmetic instructions use the REG format and can operate on local or global registers The following subsections describe arithmetic instructions for ordinal and integer data types Table 5 3 Arithmetic Operations Arithmetic Operations Data Types Integer Ordinal Add X X Add with Carry X X Conditional Add X X Subtract X X Su...

Page 94: ... 2 3 2 Remainder and Modulo These instructions divide one operand by another and retain the remainder of the operation The difference between the remainder and modulo instructions lies in the sign of the result For remi and remo the result has the same sign as the dividend for modi the result has the same sign as the divisor addi Add Integer addo Add Ordinal ADD cc conditional add subi Subtract In...

Page 95: ...scarding the bits shifted out has the effect of rounding the result toward negative shrdi is provided for dividing integers by the power of 2 With this instruction 1 is added to the result when the bits shifted out are non zero and the operand is negative which produces the correct result for negative operands shli and shrdi are equivalent to muli and divi by the power of 2 respectively except in ...

Page 96: ...0 of the condition codes when the operation would have resulted in an integer overflow condition This facilitates a software implementation of extended integer arithmetic emul multiplies two ordinals each contained in a register producing a long ordinal result stored in two registers ediv divides a long ordinal by an ordinal producing an ordinal quotient and an ordinal remainder stored in two adja...

Page 97: ...s The two bit field instructions are extract and modify extract converts a specified bit field taken from an ordinal value into an ordinal value In essence this instruction shifts right a bit field in a register and fills in the bits to the left of the bit field with zeros eshro also provides the equivalent of a 64 bit extract of 32 bits modify copies bits from one register into another register O...

Page 98: ...as with cmpi and cmpo When set no comparison is performed and the condition code flags are not changed The conditional compare instructions are provided specifically to optimize two sided range comparisons to check when A is between B and C i e B A C Here a compare instruction cmpi or cmpo checks one side of the range e g A B and a conditional compare instruction concmpi or concmpo checks the othe...

Page 99: ...ative loops 5 2 6 3 Test Condition Codes These test instructions allow the state of the condition code flags to be tested When the condition code matches the instruction specified condition a TRUE 0000 0001H is stored in a destination register otherwise a FALSE 0000 0000H is stored All use the COBR format and can operate on local and global registers cmpinci compare and increment integer cmpinco c...

Page 100: ...two instructions perform the same function however their determination of the target IP differs The target IP of a b instruction is specified at link time as a relative displacement from the current IP The target IP of the bx instruction is the absolute address resulting from the instruction s use of a memory addressing mode during execution bal and balx store the next instruction s address in a s...

Page 101: ...er compare ordinal and branch on bit be branch if equal true bne branch if not equal bl branch if less ble branch if less or equal bg branch if greater bge branch if greater or equal bo branch if ordered bno branch if unordered false cmpibe compare integer and branch if equal cmpibne compare integer and branch if not equal cmpibl compare integer and branch if less cmpible compare integer and branc...

Page 102: ...anism for making procedure calls Refer to section 7 1 CALL AND RETURN MECHANISM pg 7 2 The following instructions support this mechanism call and ret use the CTRL machine instruction format callx uses the MEM format and can specify local or global registers calls uses the REG format and can specify local or global registers call and callx make local calls to procedures A local call is a call that ...

Page 103: ...o return from all calls including local and supervisor calls and from implicit calls to interrupt and fault handlers 5 2 9 Faults Generally the processor generates faults automatically as the result of certain operations Fault handling procedures are then invoked to handle various fault types without explicit intervention by the currently running program These conditional fault instructions permit...

Page 104: ...e event generation This instruction is used in part to load and control the i960 Jx processor s breakpoint registers 5 2 11 Atomic Instructions Atomic instructions perform an atomic read modify write operation on operands in memory An atomic operation is one in which other memory operations are forced to occur before or after but not during the accesses that comprise the atomic operation These ins...

Page 105: ...struction however it is implicitly accessed by instructions that use the condition codes or set the integer overflow flag sysctl is used to configure the interrupt controller breakpoint registers and instruction cache It also permits software to signal an interrupt or cause a processor reset and reinitialization sysctl may be executed only by programs operating in supervisor mode halt puts the pro...

Page 106: ... misses the data cache the processor does not stall the issuing of subsequent instructions other than stores that do not depend on the load Software should avoid following a load with an instruction that depends on the result of the load For a load that hits the data cache there is a one cycle stall when the instruction immediately after the load requires the data When the load fails to hit the da...

Page 107: ...div Once issued these MDU instructions are executed in parallel with other non MDU instructions that do not depend on the result of the MDU operation Attempting to issue another MDU instruction while a current MDU instruction is executing stalls the processor until the first one completes 5 3 1 5 Multi Cycle Register Operations A few register operations can also take multiple cycles The following ...

Page 108: ...ycles to execute and one more cycle to fetch the target instruction when the branch is actually taken The instructions are 5 3 1 7 Memory Instructions The i960 Jx processor provides efficient support for naturally aligned byte short and word accesses that use one of 6 optimized addressing modes These accesses require only 1 to 2 cycles to execute additional cycles are needed for a load to return i...

Page 109: ...for MDU Instructions When performing a call operation or delivering an interrupt the processor typically attempts to push the first four local registers pfp sp rip and r3 onto the local register cache as early as possible Because of register interlock this operation stalls until previous instructions return their results to these registers In most cases this is not a problem however in the case of...

Page 110: ...as completed This ensures that a fault from the previous instruction is delivered before the next instruction can begin execution Imprecise fault mode allows new instructions to be issued before previous ones have completed thus increasing the instruction issue rate Many applications can tolerate the imprecise fault reporting for the performance gain When necessary a syncf can be used in imprecise...

Page 111: ...6 INSTRUCTION SET REFERENCE ...

Page 112: ......

Page 113: ...nstruction format APPENDIX B OPCODES AND EXECUTION TIMES A quick reference listing of instruction encodings assists debugging with a logic analyzer APPENDIX C MACHINE LEVEL INSTRUCTION FORMATS Describes instruction set opword encodings i960 Jx PROCESSOR INSTRUCTION SET QUICK REFERENCE order number 272597 A pocket sized quick reference to all instructions 6 1 NOTATION In general notation in this ch...

Page 114: ...s are not typically portable to earlier i960 processor family imple mentations such as the i960 Kx microprocessors 6 1 2 Mnemonic The Mnemonic section gives the mnemonic in boldface type and instruction name for each instruction covered on the page for example subi Subtract Integer This mnemonic is the actual assembly language instruction name recognized by assemblers 6 1 3 Format The Format secti...

Page 115: ... function and operands It also gives programming hints when appropriate 6 1 5 Action The Action section gives an algorithm written in a C like pseudo code that describes direct effects and possible side effects of executing an instruction Algorithms document the instruction s net effect on the programming environment they do not necessarily describe how the processor actually implements the instru...

Page 116: ...Addition Subtraction Multiplication Integer or Ordinal Division Integer or Ordinal Comment delimiter Table 6 2 Faults Applicable to All Instructions Fault Type Subtype Description TRACE MARK A Mark Trace Event is signaled after completion of an instruction for which there is a hardware breakpoint condition match A Trace fault is generated when TC mk is set INSTRUCTION An Instruction Trace Event is...

Page 117: ...ons Fault Type Subtype Description OPERATION UNALIGNED Any instruction that causes an unaligned memory access causes an operation aligned fault when unaligned faults are not masked in the fault configuration word in the Processor Control Block PRCB INVALID_OPCODE This fault is generated when the processor attempts to execute an instruction containing an undefined opcode or addressing mode INVALID_...

Page 118: ...or more information on the formats 6 1 9 See Also The See Also section gives the mnemonics of related instructions which are also alphabetically listed in this chapter 6 1 10 Side Effects This section indicates whether the instruction causes changes to the condition code bits in the Arithmetic Controls 6 1 11 Notes This section provides additional information about an instruction such as whether i...

Page 119: ...dd Integer if Ordered Format add src1 src2 dst reg lit reg lit reg Description Conditionally adds src2 and src1 values and stores the result in dst based on the AC register condition code When for Unordered the condition code is 0 or when for all other cases the logical AND of the condition code and the mask part of the opcode is not 0 then the values are added and placed in the destination Otherw...

Page 120: ...AC om 1 AC of 1 else generate_fault ARITHMETIC OVERFLOW Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 ARITHMETIC OVERFLOW Occurs only with addi cc Example Assume AC cc AND 0012 0 addig r4 r8 r10 r10 r8 r4 Assume AC cc AND 1012 0 addone r4 r8 r10 r10 is not changed addone 1012 Not equal addine addole 1102 Less or equal addile addoo 1112 Ordered addio Table 6 4 Condition Code Mask Description...

Page 121: ...ddol 7C0H REG addone 7D0H REG addole 7E0H REG addoo 7F0H REG addino 781H REG addig 791H REG addie 7A1H REG addige 7B1H REG addil 7C1H REG addine 7D1H REG addile 7E1H REG addio 7F1H REG See Also addc SUB cc addi addo Notes This class of core instructions is not implemented on 80960Cx Kx and Sx processors ...

Page 122: ...nd integer source operands Instead the processor evaluates the result for both data types and sets condition code bits 0 and 1 accordingly An integer overflow fault is never signaled with this instruction Action dst src1 src2 AC cc 1 31 0 AC cc 2 0 0002 if src2 31 src1 31 src2 31 dst 31 AC cc 0 1 Set overflow bit AC cc 1 src2 src1 AC cc 1 32 Carry out Faults STANDARD Refer to section 6 1 6 Faults ...

Page 123: ...ical The only difference is that addi can signal an integer overflow Action addo dst src2 src1 31 0 addi true_result src1 src2 dst true_result 31 0 if true_result 2 31 1 true_result 2 31 Check for overflow if AC om 1 AC of 1 else generate_fault ARITHMETIC OVERFLOW Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 ARITHMETIC OVERFLOW Occurs only with addi Example addi r4 g5 r9 r9 g5 r4 Opcode ad...

Page 124: ... When condition code is X1X2 bit 1 1 the selected bit is set otherwise it is cleared Typically this instruction is used to set the bitpos bit in the targ register when the result of a compare instruction is the equal condition code 0102 Action if AC cc 0102 0 dst src 2 bitpos 32 else dst src 2 bitpos 32 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example Assume AC cc 0102 alterbit 24 g4 g...

Page 125: ...sult in dst Note in the action expressions below src2 operand comes first so that with andnot the expression is evaluated as src2 and not src1 rather than src1 and not src2 Action and dst src2 src1 andnot dst src2 src1 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example and 0x7 g8 g2 Put lower 3 bits of g8 in g2 andnot 0x7 r12 r9 Copy r12 to r9 with lower three bits cleared Opcode and 581...

Page 126: ...from accessing the word of memory containing the word specified by src dst operand until operation completes See section 3 5 1 Memory Requirements pg 3 14 or more information on atomic accesses Memory location in addr is the word s first byte LSB address Address is automatically aligned to a word boundary Note that addr operand maps to src1 operand of the REG format Action implicit_syncf tempa add...

Page 127: ... 3 14 or more information on atomic accesses Memory read and write are done atomically i e other bus masters must be prevented from accessing the word of memory containing the word specified with the src dst operand until operation completes Memory location in addr is the modified word s first byte LSB address Address is automatically aligned to a word boundary Action implicit_syncf tempa addr 0xF...

Page 128: ...ve address which allows the full range of addressing modes to be used to specify target instruction s IP The IP displacement addressing mode allows the instruction to be IP relative Indirect branching can be performed by placing target address in a register then using a register indirect addressing mode Refer to section 2 3 MEMORY ADDRESSING MODES pg 2 6 for information on this subject Action b te...

Page 129: ...4 bytes from current IP When using the Intel i960 processor assembler targ must be a label which specifies the target instruction s IP balx performs same operation as bal except next instruction address is stored in dst allowing the return IP to be stored in any available register With balx the full address space can be accessed Here the target operand is an effective address which allows full ran...

Page 130: ...ET REFERENCE 6 18 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example bal xyz g14 IP 4 IP xyz balx g2 g4 g4 IP 4 IP g2 Opcode bal 0BH CTRL balx 85H MEM See Also b bx BRANCH cc COMPARE AND BRANCH cc bbc bbs ...

Page 131: ...targ otherwise it sets condition code to 0102 and goes to next instruction For bbs when selected bit is set the processor sets condition code to 0102 and branches to targ otherwise it sets condition code to 0002 and goes to next instruction targ can be no farther than 212 to 212 4 bytes from current IP When using the Intel i960 processor assembler targ must be a label which specifies target instru...

Page 132: ...sume bit 10 of r6 is clear bbc 10 r6 xyz Bit 10 of r6 is checked and found clear AC cc 000 IP xyz Opcode bbc 30H COBR bbs 37H COBR See Also chkbit COMPARE AND BRANCH cc BRANCH cc Side Effects Sets the condition code in the arithmetic controls ...

Page 133: ... it goes to next instruction For bno the processor branches to instruction specified with targ when the condition code is zero Otherwise it goes to next instruction For instance bno unordered can be used as a branch when false instruction when coupled with chkbit For bno branch is taken when condition code equals 0002 be can be used as branch if true instruction The targ operand value can be no fa...

Page 134: ... 2 IP 31 2 IP 31 2 temp 31 2 IP 1 0 0 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example Assume AC cc AND 1002 0 bl xyz IP xyz Opcode be 12H CTRL bne 15H CTRL bl 14H CTRL ble 16H CTRL bg 11H CTRL bge 13H CTRL bo 17H CTRL bno 10H CTRL See Also b bx bbc bbs COMPARE AND BRANCH cc bal balx ...

Page 135: ...ng order of the bytes Byte 0 of src becomes byte 3 of dst byte 1 of src becomes byte 2 of dst etc Action dst rotate_left src 8 0x00FF00FF rotate_left src 24 0xFF00FF00 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example g8 0x89ABCDEF bswap g8 g10 Reverse byte order g10 0xEFCDAB89 Opcode bswap 5ADH REG See Also scanbyte rotate Notes This core instruction is not implemented on Cx Kx and Sx ...

Page 136: ... stack frame for the called procedure Processor then goes to the instruction specified with targ and begins execution targ can be no farther than 223 to 223 4 bytes from current IP Action Wait for any uncompleted instructions to finish implicit_syncf temp SP SALIGN 16 1 SALIGN 16 1 Round stack pointer to next boundary SALIGN 1 on i960 Jx processors RIP IP if register_set_available allocate_new_fra...

Page 137: ...essor also allocates a new set of local registers and a new stack frame for the called procedure When the processor switches to supervisor mode the new stack frame is created on the supervisor stack Action Wait for any uncompleted instructions to finish implicit_syncf If targ 259 generate_fault PROTECTION LENGTH temp get_sys_proc_entry sptbase 48 4 targ sptbase is address of supervisor procedure t...

Page 138: ...P FP PFP rrr temp RRR FP tempa SP tempa 64 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 PROTECTION LENGTH Specifies a procedure number greater than 259 Example calls r12 IP value obtained from procedure table for procedure number given in r12 calls 3 Call procedure 3 Opcode calls 660H REG See Also bal call callx ret ...

Page 139: ... type which allows the full range of addressing modes to be used to specify the IP of the target instruction The IP displacement addressing mode allows the instruction to be IP relative Indirect calls can be performed by placing the target address in a register and then using one of the register indirect addressing modes Refer to CHAPTER 2 DATA TYPES AND MEMORY ADDRESSING MODES for more informatio...

Page 140: ...INSTRUCTION SET REFERENCE 6 28 Example callx g5 IP g5 where the address in g5 is the address of the new procedure Opcode callx 86H MEM See Also bal call calls ret ...

Page 141: ...When bit is set condition code is set to 0102 when bit is clear condition code is set to 0002 Action if src2 2 bitpos 32 0 AC cc 0002 else AC cc 0102 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example chkbit 13 g8 Checks bit 13 in g8 and sets AC cc according to the result Opcode chkbit 5AEH REG See Also alterbit clrbit notbit setbit cmpi cmpo Side Effects Sets the condition code in the a...

Page 142: ...it reg lit reg Description Copies src value to dst with one bit cleared bitpos operand specifies bit to be cleared Action dst src 2 bitpos 32 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example clrbit 23 g3 g6 g6 g3 with bit 23 cleared Opcode clrbit 58CH REG See Also alterbit chkbit notbit setbit ...

Page 143: ...e intended for use in ending iterative loops For cmpdeci integer overflow is ignored to allow looping down through the minimum integer values Action if src1 src2 AC cc 1002 else if src1 src2 AC cc 0102 else AC cc 0012 dst src2 1 Overflow suppressed for cmpdeci Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example cmpdeci 12 g7 g1 Compares g7 with 12 and sets AC cc to indicate the result g1 ...

Page 144: ...d for use in ending iterative loops For cmpinci integer overflow is ignored to allow looping up through the maximum integer values Action if src1 src2 AC cc 1002 else if src1 src2 AC cc 0102 else AC cc 0012 dst src2 1 Overflow suppressed for cmpinci Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example cmpinco r8 g2 g9 Compares the values in g2 and r8 and sets AC cc to indicate the result g...

Page 145: ...lowed by a branch if instruction is equivalent to a compare integer and branch instruction The latter method of comparing and branching produces more compact code however the former method can execute byte and short compares without masking The same is true for cmpo and the compare ordinal and branch instructions Action For cmpo cmpi N 31 For cmpos cmpis N 15 For cmpob cmpib N 7 if src1 N 0 src2 N...

Page 146: ...as greater than 0x10 Opcode cmpi 5A1H REG cmpib 595H REG cmpis 597H REG cmpo 5A0H REG cmpob 594H REG cmpos 596H REG See Also COMPARE AND BRANCH cc cmpdeci cmpdeco cmpinci cmpinco concmpi concmpo Side Effects Sets the condition code in the arithmetic controls Notes The core instructions cmpib cmpis compob and compos are not imple mented on 80960Cx Kx and Sx processors ...

Page 147: ...ch If Less Or Equal cmpobg Compare Ordinal and Branch If Greater cmpobge Compare Ordinal and Branch If Greater Or Equal Format cmpib src1 src2 targ reg lit reg disp cmpob src1 src2 targ reg lit reg disp Description Compares src2 and src1 values and sets AC register condition code according to comparison results When logical AND of condition code and mask part of opcode is not zero the processor br...

Page 148: ... Assume g3 g9 cmpibl g3 g9 xyz g9 is compared with g3 IP xyz assume 19 r7 cmpobge 19 r7 xyz 19 is compared with r7 IP xyz Table 6 9 Condition Code Mask Descriptions Instruction Mask Branch Condition cmpibno 0002 No Condition cmpibg 0012 src1 src2 cmpibe 0102 src1 src2 cmpibge 0112 src1 src2 cmpibl 1002 src1 src2 cmpibne 1012 src1 src2 cmpible 1102 src1 src2 cmpibo 1112 Any Condition cmpobg 0012 sr...

Page 149: ...OBR cmpible 3EH COBR cmpibg 39H COBR cmpibge 3BH COBR cmpibo 3FH COBR cmpibno 38H COBR cmpobe 32H COBR cmpobne 35H COBR cmpobl 34H COBR cmpoble 36H COBR cmpobg 31H COBR cmpobge 33H COBR See Also BRANCH cc cmpi cmpo bal balx Side Effects Sets the condition code in the arithmetic controls ...

Page 150: ...alues The example below illustrates this application by testing whether g3 value is between g5 and g6 values where g5 is assumed to be less than g6 First a comparison cmpo of g3 and g6 is performed When g3 is less than or equal to g6 i e condition code is either 0102 or 0012 a conditional comparison concmpo of g3 and g5 is then performed When g3 is greater than or equal to g5 indicating that g3 is...

Page 151: ...REG See Also cmpo cmpi cmpdeci cmpdeco cmpinci cmpinco COMPARE AND BRANCH cc Side Effects Sets the condition code in the arithmetic controls Table 6 10 concmpo example register ordering and CC Order CC g5 g6 g3 1002 g5 g6 g3 0102 g5 g3 g6 0102 g5 g3 g6 0102 g3 g5 g6 0012 ...

Page 152: ...eded by the operation the processor orders the effects of the operation with previous and subsequent operations to ensure correct behavior Table 6 11 dcctl Operand Fields Function src1 src2 src dst Disable D cache 0 NA NA Enable D cache 1 NA NA Global invalidate D cache 2 NA NA Ensure cache coherency1 3 NA NA Get D cache status 4 NA src NA dst Receives D cache status see Figure 6 1 Reserved 5 NA N...

Page 153: ... src1 Format 28 27 16 15 12 8 4 0 31 src dst Format for Data Cache Status 3 7 11 Enabled 1 Disabled 0 of Ways 1 0 31 src dst Format for Store Data Cache Sets to Memory 16 15 Starting Set Ending Set Function Type Reserved Initialize to 0 log2 of Sets log2 Atoms Line log2 Bytes Atom 2 2 ...

Page 154: ...1 Direct 1 Direct cache size 1 Kbytes 2 Kbytes full 4 Kbytes Status 0 enable disable 0 or 1 0 or 1 0 or 1 Status 1 3 reserved 0 0 0 Status 7 4 log2 bytes per atom 2 2 2 Status 11 8 log2 atoms per line 2 2 2 Status 15 12 log2 number of sets 6 7 full 8 full Status 27 16 number of ways 1 0 0 0 0 Destination Address DA Tag Starting set DA 4H Valid Bits Starting set DA 8H Word 0 DA CH Word 1 DA 10H Wor...

Page 155: ...lues 5 Valid Bit for Word 2 of current Set and Way Valid Bit for Word 3 of current Set and Way Valid Bit for Word 1 of current Set and Way Tag Valid Bit for current Set and Way Valid Bit for Word 0 of current Set and Way 0 31 80960JA Cache Tag Format 1 Kbyte Cache 22 21 80960JA Actual Address Bits 31 10 0 31 80960JT Actual Address Bits 31 12 80960JT Cache Tag Format 4 Kbyte Cache 20 19 ...

Page 156: ...validate_Dcache break case 3 Ensure coherency of data cache with memory Causes data cache to be invalidated on this processor ensure_Dcache_coherency break case 4 Get data cache status into src_dst if Dcache_enabled src_dst 0 1 else src_dst 0 0 Atom is 4 bytes src_dst 7 4 log2 bytes per atom 4 atoms per line src_dst 11 8 log2 atoms per line src_dst 15 12 log2 number of sets src_dst 27 16 number of...

Page 157: ...way numb_ways way memory memadr tags set way memadr 4 memory memadr valid_bits set way memadr 4 for word 0 word words_in_line word memory memadr Dcache_line set way word memadr 4 break case 8 invalidate the lines that came from LMTs that had DCIIR set at the time the line was allocated NOTE for compatibility with future products that have several independent regions the value of src2 should be one...

Page 158: ...esponding word valid bit is cleared after function 6 completes to ensure data cache coherency Thus dcctl function 6 can alter the state of the cache after it completes but only the word valid bits In all cases even when the cache sets to store to external memory overlap the cache sets that map the target range in external memory DCCTL function 6 always returns the state of the cache as it existed ...

Page 159: ... src1 divi if src1 0 dst undefined_value generate_fault ARITHMETIC ZERO_DIVIDE else if src2 2 31 src1 1 dst 2 31 if AC om 1 AC of 1 else generate_fault ARITHMETIC OVERFLOW else dst src2 src1 Faults STANDARD Refer to Section 6 1 6 on page 6 5 ARITHMETIC ZERO_DIVIDE The src1 operand is 0 ARITHMETIC OVERFLOW Result too large for destination register divi only When overflow occurs and AC om 1 fault is...

Page 160: ...d register dst must be an even numbered register i e g0 g2 r4 r6 r8 This instruction performs ordinal arithmetic When this operation overflows quotient or remainder do not fit in 32 bits no fault is raised and the result is undefined Action if reg_number src2 2 0 reg_number dst 2 0 dst 0 undefined_value dst 1 undefined_value generate_fault OPERATION INVALID_OPERAND else if src1 0 dst 0 undefined_v...

Page 161: ...lower numbered register which receives the result s least significant bits dst must be an even numbered register i e g0 g2 r4 r6 r8 This instruction performs ordinal arithmetic Action if reg_number dst 2 0 dst 0 undefined_value dst 1 undefined_value generate_fault OPERATION INVALID_OPERAND else dst 0 src1 src2 31 0 dst 1 src1 src2 63 32 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example ...

Page 162: ...en numbered register i e r4 r6 r8 or g0 g2 src1 operand is a single 32 bit register or literal where the lower 5 bits specify the number of places that the src2 operand is to be shifted The least significant 32 bits of the shift operation result are stored in dst Action if reg_number src2 2 0 dst 0 undefined_value dst 1 undefined_value generate_fault OPERATION INVALID_OPERAND else dst shift_right ...

Page 163: ...ight and zero fills bits to left of shifted bit field bitpos value specifies the least significant bit of the bit field to be shifted len value specifies bit field length Action src_dst src_dst min bitpos 32 0xFFFFFFFF len Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example extract 5 12 g4 g4 g4 with bits 5 through 16 shifted right Opcode extract 651H REG See Also modify ...

Page 164: ...ual to 0002 faulto and faultno are provided for use by implementations with a floating point coprocessor They are used for compare and branch or fault operations involving real numbers The following table shows the condition code mask for each instruction The mask is opcode bits 0 2 Action For all except faultno if mask AC cc 0002 generate_fault CONSTRAINT RANGE faultno if AC cc 0002 generate_faul...

Page 165: ...STRAINT RANGE When condition being tested is true Example Assume AC cc AND 1102 0002 faultle Generate CONSTRAINT_RANGE fault Opcode faulte 1AH CTRL faultne 1DH CTRL faultl 1CH CTRL faultle 1EH CTRL faultg 19H CTRL faultge 1BH CTRL faulto 1FH CTRL faultno 18H CTRL See Also BRANCH cc TEST cc ...

Page 166: ...hed a flushreg must be executed prior to modifying the PFP to return to a frame other than the one directly below the current frame To reduce interrupt latency flushreg is abortable When an interrupt of higher priority than the current process is detected while flushreg is executing flushreg flushes at least one frame and aborts After executing the interrupt handler the processor returns to the fl...

Page 167: ... the Process Controls is set For more information on trace fault generation refer to CHAPTER 9 TRACING AND DEBUGGING Action A mark trace event is generated independent of the setting of the mark trace mode flag Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 TRACE MARK A TRACE MARK fault is generated if PC te 1 Example Assume PC te 1 fmark Mark trace event is generated at this point in the in...

Page 168: ...f Halt mode execution resumes at the instruction immediately after the halt instruction The processor must be in supervisor mode to use this instruction Action implicit_syncf if PC em supervisor generate_fault TYPE MISMATCH switch src1 case 0 Disable interrupts set ICON gie global_interrupt_enable true break case 1 Enable interrupts clear ICON gie global_interrupt_enable false break case 2 Use the...

Page 169: ...mpt to execute instruction while not in supervisor mode Example ICON gie 1 g0 1 Interrupts disabled halt g0 Enable interrupts and halt Opcode halt 65DH REG Notes This instruction is implemented on the 80960Rx and 80960Jx processor fam ilies only and may or may not be implemented on future i960 processors ...

Page 170: ...e processor orders the effects of the operation with previous and subsequent operations to ensure correct behavior For specific function setup see the following tables and diagrams Table 6 15 icctl Operand Fields Function src1 src2 src dst Disable I cache 0 NA NA Enable I cache 1 NA NA Invalidate I cache 2 NA NA Load and lock I cache 3 src Starting address of code to lock Number of ways to lock Ge...

Page 171: ... I cache Status 3 7 11 Enabled 1 Disabled 0 log2 of Sets of Ways 1 8 7 0 31 src dst Format for I cache Locking Status 24 23 of ways that Lock Way Size in Words 0 31 src dst Format for Store I cache Sets to Memory 16 15 Starting Set Ending Set of ways that Reserved Initialize to 0 log2 Atoms Line log2 Bytes Atom are currently locked Constants 0FFFH 04H ...

Page 172: ...f ways 2 2 2 cache size 2 Kbytes 4 Kbytes 16 Kbytes Status 0 enable disable 0 or 1 0 or 1 0 or 1 Status 1 3 reserved 0 0 0 Status 7 4 log2 bytes per atom 2 2 2 Status 11 8 log2 atoms per line 2 2 2 Status 15 12 log2 number of sets 6 7 9 Status 27 16 number of ways 1 1 1 1 Lock Status 7 0 number of blocks that lock 1 1 1 Lock Status 23 8 block size in words 256 512 2048 Lock Status 31 24 number of ...

Page 173: ...ss DA Tag Starting set DA 4H Valid Bits Starting set DA 8H Word 0 DA CH Word 1 DA 10H Word 2 DA 14H Word 3 DA 18H Tag Starting set DA 1CH Valid Bits Starting set DA 20H Word 0 DA 24H Word 1 DA 28H Word 2 DA 2CH Word 3 DA 30H Set_Data Starting Set 1 DA 34H Tag Starting set 1 DA 38H Valid Bits Starting set 1 DA 3CH Way 0 Way 1 Way 0 ...

Page 174: ...its Values 5 I Cache Set Data Value Valid Bit for Word 2 of current Set and Way Valid Bit for Word 3 of current Set and Way Valid Bit for Word 1of current Set and Way Tag Valid bit for current Set and Way Valid Bit for Word 0 of current Set and Way 0 31 80960JA Cache Tag Format 2 Kbyte Cache 22 21 80960JA Actual Address Bits 31 10 1 Way 1 is least recently used 0 31 80960JT Actual Address Bits 31 ...

Page 175: ...0 Jx src2 is aligned to a quad word boundary aligned_addr src2 0xFFFFFFF0 invalidate I cache unlock I cache for j 0 j src_dst j way way_associated_with_block j start src2 j block_size end start block_size for i start i end i i 4 set set_associated_with i word word_associated_with i Icache_line set way word memory i update_tag_n_valid_bits set way word lock_icache set way word break case 4 Get inst...

Page 176: ...ate_fault OPERATION INVALID_OPERAND memadr src2 Must be word aligned if 0x3 memadr 0 generate_fault OPERATION INVALID_OPERAND for set start set end set Set_Data is described at end of this code flow memory memadr Set_Data set memadr 4 for way 0 way numb_ways way memory memadr tags set way memadr 4 memory memadr valid_bits set way memadr 4 for word 0 word words_in_line word memory memadr Icache_lin...

Page 177: ... Load and lock 1 block of cache one way with location of code at starting 0x10000000 Opcode icctl 65BH REG See Also sysctl Notes This instruction is implemented on the 80960Rx 80960Hx and 80960Jx pro cessor families only and may or may not be implemented on future i960 pro cessors ...

Page 178: ... This instruction is implemented by manip ulating ICON gie Action if PC em supervisor generate_fault TYPE MISMATCH old_interrupt_enable global_interrupt_enable switch src1 case 0 Disable Set ICON gie to one globally_disable_interrupts global_interrupt_enable false order_wrt subsequent_instructions break case 1 Enable Clear ICON gie to zero globally_enable_interrupts global_interrupt_enable true or...

Page 179: ...ruction while not in supervisor mode Example ICON gie 0 interrupts enabled intctl 0 g4 Disable interrupts ICON gie 1 g4 1 Opcode intctl 658H REG See Also intdis inten Notes This instruction is implemented on the 80960Rx 80960Hx and 80960Jx pro cessor families only and may or may not be implemented on future i960 pro cessors ...

Page 180: ...lemented by setting ICON gie to one globally_disable_interrupts global_interrupt_enable false order_wrt subsequent_instructions Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 TYPE MISMATCH Attempt to execute instruction while not in supervisor mode Example ICON gie 0 interrupts enabled intdis Disable interrupts ICON gie 1 Opcode intdis 5B4H REG See Also intctl inten Notes This instruction is...

Page 181: ...lemented by clearing ICON gie to zero globally_enable_interrupts global_interrupt_enable true order_wrt subsequent_instructions Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 TYPE MISMATCH Attempt to execute instruction while not in supervisor mode Example ICON gie 1 interrupts disabled inten Enable interrupts ICON gie 0 Opcode inten 5B5H REG See Also intctl intdis Notes This instruction is ...

Page 182: ...s ldob and ldib load a byte and ldos and ldis load a half word and convert it to a full 32 bit word Data being loaded is sign extended during integer loads and zero extended during ordinal loads ld ldl ldt and ldq instructions copy 4 8 12 and 16 bytes respectively from memory into successive registers For ldl dst must specify an even numbered register i e g0 g2 For ldt and ldq dst must specify a r...

Page 183: ...sm See section 2 2 2 Byte Ordering pg 2 4 if dst 15 02 dst 31 16 0x0000 else dst 31 16 0xFFFF if effective_address 0 02 unaligned_fault_enabled generate_fault OPERATION UNALIGNED ldl if reg_number dst 2 0 generate_fault OPERATION INVALID_OPERAND dst not modified else dst read_memory effective_address 31 0 dst_ _1 read_memory effective_address_ _4 31 0 if effective_address 2 0 0002 unaligned_fault_...

Page 184: ... 2 2 2 Byte Ordering pg 2 4 dst_ _1 read_memory effective_adddress_ _4 31 0 dst_ _2 read_memory effective_adddress_ _8 31 0 dst_ _3 read_memory effective_adddress_ _12 31 0 if effective_address 3 0 00002 unaligned_fault_enabled generate_fault OPERATION UNALIGNED Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 OPERATION UNALIGNED OPERATION INVALID_OPERAND Example ldl 2450 r3 r10 r10 r11 r3 245...

Page 185: ...or validity Any addressing mode may be used to calculate efa An important application of this instruction is to load a constant longer than 5 bits into a register To load a register with a constant of 5 bits or less mov can be used with a literal as the src operand Action dst effective_address Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example lda 58 g9 g1 g1 g9 58 lda 0x749 r8 r8 0x749 ...

Page 186: ...de is not enabled mark behaves like a no op For more information on trace fault generation refer to CHAPTER 9 TRACING AND DEBUGGING Action if PC te TC mk generate_fault TRACE MARK Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 TRACE MARK Trace fault is generated if PC te 1 and TC mk 1 Example Assume that the mark trace mode is enabled ld xyz r4 addi r4 r5 r6 mark Mark trace event is generate...

Page 187: ...er mask specifies bits that may be changed Only bits set in mask are modified Once the AC register is changed its initial state is copied into dst Action temp AC AC src mask AC mask dst temp Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example modac g1 g9 g12 AC g9 masked by g1 g12 initial value of AC Opcode modac 645H REG See Also modpc modtc Side Effects Sets the condition code in the ar...

Page 188: ... src1 Action if src1 0 dst undefined_value generate_fault ARITHMETIC ZERO_DIVIDE dst src2 src2 src1 src1 if src2 src1 0 dst 0 dst dst src1 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 ARITHMETIC ZERO_DIVIDE The src1 operand is zero Example modi r9 r2 r5 r5 modulo r2 r9 Opcode modi 749H REG See Also divi divo remi remo Notes modi generates the correct result 0 when computing 231 mod 1 altho...

Page 189: ...fies selected bits in src dst with bits from src The mask operand selects the bits to be modified only bits set in the mask operand are modified in src dst Action src_dst src mask src_dst mask Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example modify g8 g10 r4 r4 g10 masked by g8 Opcode modify 650H REG See Also alterbit extract ...

Page 190: ...sed to read the process controls without the processor being in supervisor mode When the action of this instruction lowers the processor priority the processor checks the interrupt table for pending interrupts When process controls are changed the processor recognizes the changes immediately except in one situation when modpc is used to change the trace enable bit the processor may not recognize t...

Page 191: ...lso modac modtc Notes Since modpc does not switch stacks it should not be used to switch the mode of execution from supervisor to user the supervisor stack can get corrupted in this case The call and return mechanism should be used instead ...

Page 192: ...hanged trace controls may take effect immediately or may be delayed When delayed the changed trace controls may not take effect until after the first non branching instruction is fetched from memory or after four non branching instructions are executed For more information on the trace controls refer to CHAPTER 8 FAULTS and CHAPTER 9 TRACING AND DEBUGGING Action mode_bits 0x000000FE event_flags 0X...

Page 193: ... src1 and dst registers must be even numbered e g g0 g2 or r4 r6 for movl and an integral multiple of four e g g0 g4 or r4 r8 for movt and movq The moved register values are unpredictable when 1 the src and dst operands overlap 2 registers are not properly aligned Action mov if is_reg src1 dst src1 else dst 4 0 src1 src1 is a 5 bit literal dst 31 5 0 movl if reg_num src1 2 0 reg_num dst 2 0 dst un...

Page 194: ...l dst 31 5 0 dst_ _1 31 0 0 dst_ _2 31 0 0 movq if reg_num src1 4 0 reg_num dst 4 0 dst undefined_value dst_ _1 undefined_value dst_ _2 undefined_value dst_ _3 undefined_value generate_fault OPERATION INVALID_OPERAND else if is_reg src1 dst src1 dst_ _1 src1_ _1 dst_ _2 src1_ _2 dst_ _3 src1_ _3 else dst 4 0 src1 src1 is a 5 bit literal dst 31 5 0 dst_ _1 31 0 0 dst_ _2 31 0 0 dst_ _3 31 0 0 Fault...

Page 195: ...INSTRUCTION SET REFERENCE 6 83 6 Opcode mov 5CCH REG movl 5DCH REG movt 5ECH REG movq 5FCH REG See Also LOAD STORE lda ...

Page 196: ... overflow Action mulo dst src2 src1 31 0 muli true_result src1 src2 dst true_result 31 0 if true_result 2 31 1 true_result 2 31 Check for overflow if AC om 1 AC of 1 else generate_fault ARITHMETIC OVERFLOW Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 ARITHMETIC OVERFLOW Result is too large for destination register muli only When a condition of overflow occurs the least significant 32 bits ...

Page 197: ...reg lit reg Description Performs a bitwise NAND operation on src2 and src1 values and stores the result in dst Action dst src2 src1 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example nand g5 r3 r7 r7 r3 NAND g5 Opcode nand 58EH REG See Also and andnot nor not notand notor or ornot xnor xor ...

Page 198: ...lit reg Description Performs a bitwise NOR operation on the src2 and src1 values and stores the result in dst Action dst src2 src1 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example nor g8 28 r5 r5 28 NOR g8 Opcode nor 588H REG See Also and andnot nand not notand notor or ornot xnor xor ...

Page 199: ...rms a bitwise NOT not instruction or NOT AND notand instruction operation on the src2 and src1 values and stores the result in dst Action not dst src1 notand dst src2 src1 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example not g2 g4 g4 NOT g2 notand r5 r6 r7 r7 NOT r6 AND r5 Opcode not 58AH REG notand 584H REG See Also and andnot nand nor notor or ornot xnor xor ...

Page 200: ...escription Copies the src2 value to dst with one bit toggled The bitpos operand specifies the bit to be toggled Action dst src2 2 src1 32 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example notbit r3 r12 r7 r7 r12 with the bit specified in r3 toggled Opcode notbit 580H REG See Also alterbit chkbit clrbit setbit ...

Page 201: ... reg lit reg Description Performs a bitwise NOTOR operation on src2 and src1 values and stores result in dst Action dst src2 src1 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example notor g12 g3 g6 g6 NOT g3 OR g12 Opcode notor 58DH REG See Also and andnot nand nor not notand or ornot xnor xor ...

Page 202: ...orms a bitwise OR or instruction or ORNOT ornot instruction operation on the src2 and src1 values and stores the result in dst Action or dst src2 src1 ornot dst src2 src1 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example or 14 g9 g3 g3 g9 OR 14 ornot r3 r8 r11 r11 r8 OR NOT r3 Opcode or 587H REG ornot 58BH REG See Also and andnot nand nor not notand notor xnor xor ...

Page 203: ...e same as the sign of src2 Action remi remo if src1 0 generate_fault ARITHMETIC ZERO_DIVIDE dst src2 src2 src1 src1 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 ARITHMETIC ZERO_DIVIDE The src1 operand is 0 Example remo r4 r5 r6 r6 r5 rem r4 Opcode remi 748H REG remo 708H REG See Also modi Notes remi produces the correct result 0 even when computing 231 remi 1 which would cause the correspo...

Page 204: ... below the return status field and prereturn trace flag determine the action that the processor takes on the return These fields are contained in bits 0 through 3 of register r0 of the called procedure s local registers See CHAPTER 7 PROCEDURE CALLS for more on ret Action implicit_syncf if pfp p PC te TC p pfp p 0 generate_fault TRACE PRERETURN switch return_status_field case 0002 local return get...

Page 205: ...reak case 1102 reserved unpredictable behavior break case 1112 interrupt return tempa memory FP 16 tempb memory FP 12 get_FP_and_IP AC tempb if execution_mode supervisor PC tempa check_pending_interrupts break get_FP_and_IP FP PFP free current_register_set if not_allocated FP retrieve_from_memory FP IP RIP Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example ret Program control returns to ...

Page 206: ...end of word The len operand specifies number of bits that the dst operand is rotated This instruction can also be used to rotate bits to the right The number of bits the word is to be rotated right should be subtracted from 32 and the result used as the len operand Action src2 is rotated by len mod 32 This value is stored in dst Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example rotate 1...

Page 207: ...ndition code is set to 0102 When src value is zero all 1 s are stored in dst and condition code is set to 0002 Action dst 0xFFFFFFFF AC cc 0002 for i 31 i 0 i if src1 2 i 0 dst i AC cc 0102 break Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example assume g8 is nonzero scanbit g8 g10 g10 bit number of most significant set bit in g8 AC cc 0102 Opcode scanbit 641H REG See Also spanbit setbit...

Page 208: ...qual When no corresponding bytes are equal condition code is set to 0002 Action if src1 0x000000FF src2 0x000000FF src1 0x0000FF00 src2 0x0000FF00 src1 0x00FF0000 src2 0x00FF0000 src1 0xFF000000 src2 0xFF000000 AC cc 0102 else AC cc 0002 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example Assume r9 0x11AB1100 scanbyte 0x00AB0011 r9 AC cc 0102 Opcode scanbyte 5ACH REG See Also bswap Side E...

Page 209: ...code bits in the arithmetic controls When for Unordered the condition code is 0 or when for the other cases the logical AND of the condition code and the mask part of the opcode is not zero then the value of src2 is stored in the desti nation Else the value of src1 is stored in the destination Action if mask AC cc mask AC cc dst src2 else dst src1 Faults STANDARD Refer to section 6 1 6 Faults pg 6...

Page 210: ... cc 0012 sell g0 g1 g2 g2 g0 Opcode selno 784H REG selg 794H REG sele 7A4H REG selge 7B4H REG sell 7C4H REG selne 7D4H REG selle 7E4H REG selo 7F4H REG See Also MOVE TEST cc cmpi cmpo SUB cc Notes These core instructions are not implemented on 80960Cx Kx and Sx proces sors ...

Page 211: ... dst reg lit reg lit reg Description Copies src value to dst with one bit set bitpos specifies bit to be set Action dst src 2 bitpos 32 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example setbit 15 r9 r1 r1 r9 with bit 15 set Opcode setbit 583H REG See Also alterbit chkbit clrbit notbit ...

Page 212: ... An overflow fault is generated when the bits shifted out are not the same as the most significant bit bit 31 When overflow occurs dst equals src shifted left as much as possible without overflowing shri performs a conventional arithmetic shift right operation by shifting in the most significant bit bit 31 When this instruction is used to divide a negative integer operand by the power of 2 it prod...

Page 213: ...lse generate_fault ARITHMETIC OVERFLOW shri if len 32 count 32 else count src1 temp src while count 0 temp temp 1 31 0 temp 31 src 31 count count 1 dst temp shrdi dst src 2 len Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 ARITHMETIC OVERFLOW For shli Example shli 13 g4 r6 g6 g4 shifted left 13 bits Opcode shlo 59CH REG shro 598H REG shli 59EH REG shri 59BH REG shrdi 59AH REG ...

Page 214: ...vi muli rotate eshro Notes shli and shrdi are identical to multiplications and divisions for all positive and negative values of src2 shri is the conventional arithmetic right shift that does not produce a correct quotient when src2 is negative ...

Page 215: ...dition code is set to 0102 When src value is all 1 s all 1 s are stored in dst and condition code is set to 0002 Action dst 0xFFFFFFFF AC cc 0002 for i 31 i 0 i if src1 2 i 0 dst i AC cc 0102 break Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example Assume r2 is not 0xffffffff spanbit r2 r9 r9 bit number of most significant clear bit in r2 AC cc 0102 Opcode spanbit 640H REG See Also scanb...

Page 216: ... complete discussion stob and stib store a byte and stos and stis store a half word from the src register s low order bytes Data for ordinal stores is truncated to fit the destination width When the data for integer stores cannot be represented correctly in the destination width an Arithmetic Integer Overflow fault is signaled st stl stt and stq copy 4 8 12 and 16 bytes respectively from successiv...

Page 217: ... 0 end if stos if illegal_write_to_on_chip_RAM_or_MMR generate_fault TYPE MISMATCH else if effective_address 0 02 unaligned_fault_enabled store_to_memory effective_address 15 0 src1 15 0 generate_fault OPERATION UNALIGNED else store_to_memory effective_address 15 0 src1 15 0 stis if illegal_write_to_on_chip_RAM_or_MMR generate_fault TYPE MISMATCH else if effective_address 0 02 unaligned_fault_enab...

Page 218: ... reg_number src1 4 0 generate_fault OPERATION INVALID_OPERAND else if effective_address 3 0 00002 unaligned_fault_enabled store_to_memory effective_address 31 0 src1 store_to_memory effective_address 4 31 0 src1_ _1 store_to_memory effective_address 8 31 0 src1_ _2 generate_fault OPERATION UNALIGNED else store_to_memory effective_address 31 0 src1 store_to_memory effective_address 4 31 0 src1_ _1 ...

Page 219: ...ve_address 12 31 0 src1_ _3 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 ARITHMETIC OVERFLOW For stib stis Example st g2 1254 g6 Word beginning at offset 1254 g6 g2 Opcode st 92H MEM stob 82H MEM stos 8AH MEM stib C2H MEM stis CAH MEM stl 9AH MEM stt A2H MEM stq B2H MEM See Also LOAD MOVE Notes illegal_write_to_on_chip_RAM is an implementation dependent mechanism The mapping of register bi...

Page 220: ...so be used for integer subtraction Here when integer subtraction results in an overflow condition code bit 0 is set subc does not distinguish between ordinals and integers it sets condition code bits 0 and 1 regardless of data type Action dst src2 src1 1 AC cc 1 31 0 AC cc 2 0 0002 if src2 31 src1 31 src2 31 dst 31 AC cc 0 1 Overflow bit AC cc 1 src2 src1 1 AC cc 1 32 Carry out Faults STANDARD Ref...

Page 221: ...btract Integer if Not Equal subile Subtract Integer if Less or Equal subio Subtract Integer if Ordered Format sub src1 src2 dst reg lit reg lit reg Description Subtracts src1 from src2 conditionally based on the condition code bits in the arithmetic controls When for Unordered the condition code is 0 or when for the other cases the logical AND of the condition code and the mask part of the opcode ...

Page 222: ...ault ARITHMETIC OVERFLOW Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 ARITHMETIC OVERFLOW For the SUBI cc class Example AC cc 0102 suboge g0 g1 g2 g2 g1 g0 AC cc 0012 subile g0 g1 g2 g2 not modified Opcode subono 782H REG subog 792H REG suboe 7A2H REG suboge 7B2H REG subol 7C2H REG subone 7D2H REG subole 7E2H REG suboo 7F2H REG subino 783H REG subig 793H REG subie 7A3H REG subige 7B3H REG ...

Page 223: ...INSTRUCTION SET REFERENCE 6 111 6 See Also subc subi subo SEL cc TEST cc Notes These core instructions are not implemented on 80960Cx Kx and Sx proces sors ...

Page 224: ...ions are identical The only difference is that subi can signal an integer overflow Action subo dst src2 src1 31 0 subi true_result src2 src1 dst true_result 31 0 if true_result 2 31 1 true_result 2 31 Check for overflow if AC om 1 AC of 1 else generate_fault ARITHMETIC OVERFLOW Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 ARITHMETIC OVERFLOW For subi Example subi g6 g9 g12 g12 g9 g6 Opcode...

Page 225: ...ntil_all_previous_instructions_in_flow_have_completed This also means that all of the faults on these instructions have been reported Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example ld xyz g6 addi r6 r8 r8 syncf and g6 0x1f g8 The syncf instruction ensures that any faults that may occur during the execution of the ld and addi instructions occur before the and instruction is executed O...

Page 226: ... src2 and src3 operands are also interpreted depending upon the command Figure 6 7 Src1 Operand Interpretation Table 6 18 sysctl Field Definitions Message src1 src2 src dst Type Field 1 Field 2 Field 3 Field 4 Request Interrupt 0x0 Vector Number N U N U N U Invalidate Cache 0x1 N U N U N U N U Configure Instruction Cache 0x2 Cache Mode Configuration See Table 6 19 N U Cache load address N U Reinit...

Page 227: ...le_base pend_priority atomic_unlock Update internal software priority with highest priority interrupt from newly adjusted Pending Priorities word The current internal software priority is always replaced by the new computed one If there is no bit set in pending_priorities word for the current internal one then it is discarded by this action if pend_priority 0 SW_Int_Priority 0 else msb_set scan_bi...

Page 228: ...aligned to a quad word boundary aligned_addr src2 0xfffffff0 invalidate I cache unlock I cache for j 0 j number_of_blocks_that_lock j way block_associated_with_block j start src2 j block_size end start block_size for i start i end i i 4 set set_associated_with i word word_associated_with i Icache_line set way word memory i update_tag_n_valid_bits set way word lock_icache set way word break default...

Page 229: ...ilable_data_breakpoints dst 7 4 number_of_available_data_breakpoints dst 31 8 0 break default Reserved fault occurs generate_fault OPERATION INVALID_OPERAND break order_wrt subsequent_operations Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example ldconst 0x100 r6 Set up message sysctl r6 r7 r8 Invalidate I cache r7 r8 are not used ldconst 0x204 g0 Set up message type and cache configurati...

Page 230: ...e condition code and opcode mask part is not zero Otherwise the instruction stores a false 00H in dst For testno Unordered a true is stored when the condition code is 0002 otherwise a false is stored The following table shows the condition code mask for each instruction The mask is in bits 0 2 of the opcode Table 6 20 Condition Code Mask Descriptions Instruction Mask Condition testno 0002 Unordere...

Page 231: ...lue testno if AC cc 0002 src1 1 true value else src1 0 false value Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example Assume AC cc 1002 testl g9 g9 0x00000001 Opcode teste 22H COBR testne 25H COBR testl 24H COBR testle 26H COBR testg 21H COBR testge 23H COBR testo 27H COBR testno 20H COBR See Also cmpi cmpdeci cmpinci ...

Page 232: ...rms a bitwise XNOR xnor instruction or XOR xor instruction operation on the src2 and src1 values and stores the result in dst Action xnor dst src2 src1 src2 src1 xor dst src2 src1 src2 src1 Faults STANDARD Refer to section 6 1 6 Faults pg 6 5 Example xnor r3 r9 r12 r12 r9 XNOR r3 xor g1 g7 g4 g4 g7 XOR g1 Opcode xnor 589H REG xor 586H REG See Also and andnot nand nor not notand notor or ornot ...

Page 233: ...7 PROCEDURE CALLS ...

Page 234: ......

Page 235: ...on and saves a return IP Additionally the processor saves the local registers and allocates a new set of local registers and a new stack for the called procedure The saved context is restored when the return instruction ret executes In many RISC architectures a branch and link instruction is used as the base instruction for coding a procedure call The user program then handles register and stack m...

Page 236: ...to as a supervisor call 7 1 CALL AND RETURN MECHANISM At any point in a program the i960 processor has access to the global registers a local register set and the procedure stack A subset of the stack allocated to the procedure is called the stack frame When a call executes a new stack frame is allocated for the called procedure The processor also saves the current local register set freeing these...

Page 237: ... local registers often do not have to be written out to the save area in the stack frame in memory Refer to section 7 1 4 Caching Local Register Sets pg 7 7 and section 7 1 4 1 Reserving Local Register Sets for High Priority Interrupts pg 7 8 for more about local registers and procedure stack interrelations Figure 7 1 Procedure Stack Structure and Local Registers register save area Procedure Stack...

Page 238: ...k Pointer The stack pointer is the byte aligned address of the stack frame s next unused byte The stack pointer value is stored in local register r1 the stack pointer SP register The procedure stack grows upward i e toward higher addresses When a stack frame is created the processor automatically adds 64 to the frame pointer value and stores the result in the SP register This action creates the re...

Page 239: ...cessor records the call type in the return type field The processor then uses this information to select the proper return mechanism when returning to the calling procedure The use of this information is described in section 7 8 RETURNS pg 7 20 7 1 2 7 Return Instruction Pointer The actual RIP register r2 is reserved by the processor to support the call and return mechanism and must not be used by...

Page 240: ...s set according to the call type which is performed See section 7 8 RETURNS pg 7 20 4 For a local or system local call a new stack frame is allocated by using the old stack pointer value saved in step 2 This value is first rounded to the next 16 byte boundary to create a new frame pointer then stored in the FP register Next 64 bytes are added to create the new frame s register save area This value...

Page 241: ...rformed in parallel with this data movement When the number of nested procedures exceeds local register cache size local register sets must at times be saved to and restored from their associated save areas in the procedure stack Because these operations require access to external memory this local cache miss affects call and return performance When a call is made and no frames are available in th...

Page 242: ...g Local Register Sets for High Priority Interrupts To decrease interrupt latency for high priority interrupts software can limit the number of frames available to all remaining code This includes code that is either in the executing state non inter rupted or code that is in the interrupted state but has a process priority less than 28 For the purposes of discussion here this remaining code is refe...

Page 243: ...sted procedure level user stack space reserved for local register set n local register set n stored on procedure stack Spill call with no frame spill call with frame spill 1 0 3 2 1 Empty 4 3 2 1 4 3 2 5 1 0 1 0 n 2 3 4 5 6 8 6 5 4 3 2 3 4 5 6 7 8 n Frame with no sets reserved for high priority interrupts 7 8 9 5 6 7 4 5 6 6 7 8 2 1 1 2 3 2 7 7 9 ...

Page 244: ...dicate nested procedure level Local Register Cache With no sets reserved Current Local Register Set user stack space reserved for local register set n local register set n stored on procedure stack n n for high priority interrupts Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty Empty 4 3 2 ...

Page 245: ...d procedures flushreg is also used when implementing task switches in multitasking kernels The procedure stack is changed as part of the task switch To change the procedure stack flushreg is executed to update the current procedure stack and invalidate all entries in the local register cache Next the procedure stack is changed by directly modifying the FP and SP registers and executing a call oper...

Page 246: ...gister cache has already been flushed by the flushreg before only synchronization of the PFP is performed i960 processor implementations may provide other mechanisms to ensure PFP synchronization in addition to flushreg but a flushreg after a PFP modification is ensured to work on all i960 processors 7 3 PARAMETER PASSING Parameters are passed between procedures in two ways value Parameters are pa...

Page 247: ...g procedure passes a pointer to an argument list on its stack where the remaining return values are placed Example 7 2 illustrates parameter passing by value and by reference Local registers are automatically saved when a call is made Because of the local register cache they are saved quickly and with no external bus traffic The efficiency of the local register mechanism plays an important role in...

Page 248: ...placement addressing mode allows full 32 bit IP relative addressing When a local call is made with a call or callx the processor performs the same operation as described in section 7 1 3 1 Call Operation pg 7 6 The target IP for the call is derived from the instruction s operands and the new stack frame is allocated on the current stack Example of parameter passing C source int a b 10 a proc1 a 1 ...

Page 249: ...services By calling these services with a procedure number rather than a specific IP applications software does not need to be changed each time the implementation of the kernel services is modified Only the entries in the system procedure table must be changed Second the ability to switch to a different execution mode and stack with a system supervisor call allows kernel procedures and data to be...

Page 250: ...alize to 0 000H 008H 00CH 010H 02CH 034H 030H 038H 03CH 438H 43CH Entry Type 00 Local 10 Supervisor Trace Control Bit 0 31 Procedure Entry T supervisor stack pointer base procedure entry 2 procedure entry 1 procedure entry 0 procedure entry 259 Preserved address 0 31 1 2 ...

Page 251: ...upervisor mode The processor gets a pointer to this stack from the supervisor stack pointer field in the system procedure table Figure 7 4 during the reset initial ization sequence and caches the pointer internally Only the 30 most significant bits of the supervisor stack pointer are given The processor aligns this value to the next 16 byte boundary to determine the first byte of the new stack fra...

Page 252: ...xceptions When the processor is in user mode it switches to supervisor mode When a mode switch occurs SP is read from the Supervisor Stack Pointer SSP base A new frame for the called procedure is placed at the location pointed to after alignment of SP When no mode switch occurs the new frame is allocated on the current stack When a mode switch occurs the state of the trace enable bit in the PC reg...

Page 253: ...he previous 16 byte boundary 7 7 INTERRUPT AND FAULT CALLS The architecture defines two types of implicit calls that make use of the call and return mechanism interrupt handling procedure calls and fault handling procedure calls A call to an interrupt procedure is similar to a system supervisor call Here the processor obtains pointers to the interrupt procedures through the interrupt table The pro...

Page 254: ...as the trace on return flag and then replaced by the trace controls bit in the system procedure table On a return the trace enable bit s original value is restored This mechanism allows instruction tracing to be turned on or off when a supervisor mode switch occurs See section 9 5 2 1 Tracing on Explicit Call pg 9 13 prereturn trace flag PFP p is used in conjunction with call trace and prereturn t...

Page 255: ...nd link instruction The branch and link method of making procedure calls is recommended for calls to leaf procedures Leaf procedures typically call no other procedures Branch and link is the fastest way to make a call providing the calling procedure does not require its own registers or stack frame Table 7 2 Encoding of Return Status Field Return Status Field Call Type Return Action 000 Local call...

Page 256: ......

Page 257: ...8 FAULTS ...

Page 258: ......

Page 259: ...r incorrect or inappropriate results or that could cause it to choose an undesirable control path These are called fault conditions For example the architecture defines faults for divide by zero and overflow conditions on integer calculations with an inappropriate operand value As shown in Figure 8 1 the architecture defines a fault table a system procedure table a set of fault handling procedures...

Page 260: ...ner The current local registers are saved and cached on chip PFP FP and the value 001 is written to the Return Type Field Fault Call Refer to section 7 8 RETURNS pg 7 20 for more information If the fault call is a system supervisor call from user mode the processor switches to the supervisor stack otherwise SP is re aligned on the current stack The processor writes the fault record on the new stac...

Page 261: ...d subtype Text that follows the table gives column definitions Table 8 1 i960 Jx Processor Fault Types and Subtypes Fault Type Fault Subtype Fault Record Number Name Number or Bit Position Name 0H OVERRIDE NA NA See section 8 10 4 OVERRIDE Faults pg 8 26 0H PARALLEL NA NA see section 8 6 4 Parallel Faults pg 8 9 1H TRACE Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 INSTRUCTION BRANCH CALL RETURN PRER...

Page 262: ...al fault conditions Fault type and subtype encoding allows all faults to be included in the fault table those that are common to all i960 processors and those that are specific to one or more family members The fault types are used consistently for all family members For example Fault Type 4H is reserved for floating point faults Any i960 processor with floating point operations uses Entry 4H to s...

Page 263: ...ry ARITHMETIC Fault Entry OPERATION Fault Entry TRACE Fault Entry PARALLEL OVERRIDE Fault Entry Local Call Entry Fault Handler Procedure Address System Call Entry Fault Handler Procedure Number 0000 027FH n n 4 n n 4 0 1 2 0 0 1 00H 08H 10H 18H 20H 28H 30H 38H 40H 48H 50H FCH Reserved Initialize to 0 0 31 31 Fault Table 0 1 2 ...

Page 264: ...ECORD When a fault occurs the processor records information about the fault in a fault record in memory The fault handling procedure uses the information in the fault record to correct or recover from the fault condition and if possible resume program execution The fault record is stored on the same stack that the fault handling procedure will use to handle the fault local call entry type 002 Prov...

Page 265: ...ts are stored in their respective fault record fields The processor uses this information to resume program execution after the fault is handled Figure 8 3 Fault Record 0 31 PROCESS CONTROLS ADDRESS OF FAULTING INSTRUCTION n RESERVED NFP 20 NFP 16 NFP 12 NFP 8 NFP 4 OTYPE OSUBTYPE ARITHMETIC CONTROLS FTYPE n FSUBTYPE n OVERRIDE FAULT DATA FAULT DATA NFP n 1 32 NFP 24 n 32 NFP 20 n 32 NFP 12 n 32 N...

Page 266: ...an be the user stack supervisor stack or interrupt stack The fault record begins at byte address NFP 1 NFP refers to the new frame pointer that is computed by adding the memory size allocated for padding and the fault record to the previous stack pointer SP The processor calculates the new stackpointer NSP by adding 80 bytes to the NFP Figure 8 4 Storage of the Fault Record on the Stack Current Fr...

Page 267: ...tion 8 9 PRECISE AND IMPRECISE FAULTS pg 8 19 Multiple trace fault conditions on the same instruction are reported in a single trace fault record with the exception of prereturn trace which always happens alone To support multiple fault reporting the trace fault uses bit positions in the fault subtype field to indicate occurrences of multiple faults of the same type see Table 8 1 8 6 3 Multiple Tr...

Page 268: ...t handler can simply return to the next instruction not yet executed with a ret instruction Consider the following code example where the muli and the addi instructions both have overflow conditions AC om 0 AC nif 0 and both instructions are in the instruction cache at the time of their execution The addi and muli are allowed to execute in parallel when AC nif 0 because they are executed in differ...

Page 269: ... type fault subtype address of faulting instruction and the optional fault section For example if two parallel faults occur the fault record for the second fault is located from NFP 96 to NFP 65 To calculate byte offsets n indicates the fault number Thus for the second fault recorded n 2 the relationship NFP 4 n 32 reduces to NFP 72 For the i960 Jx processor a maximum of two faults are reported in...

Page 270: ...e system procedure table the processor enters system error mode Override fault conditions include PROTECTION and OPERATION UNIMPLEMENTED faults An override fault handler must be accessed through a system supervisor call Local and system local override fault handlers are not supported by the architecture and have an unpredictable behavior Tracing is disabled upon entry into the override fault handl...

Page 271: ...en working with the processor at the development level a common fault handling strategy is to save the fault and processor state information and call a debugging tool such as a monitor 8 7 2 Program Resumption Following a Fault Because of the wide variety of faults they can occur at different times with respect to the faulting instruction Before execution of the faulting instruction e g fetch from...

Page 272: ...he Return Instruction Pointer RIP is defined and the fault handler can return to the next instruction in the flow TRACE ARITHMETIC INTEGER_OVERFLOW In general resumption of program execution with no changes in the program s control flow is possible with the following fault types or subtypes All TRACE Subtypes The effect of specific fault types on a program is defined in section 8 10 FAULT REFERENC...

Page 273: ...procedure must alter the RIP To do this reliably the fault handling procedure should perform the following steps 1 Flush the local register sets to the stack with a flushreg instruction 2 Modify the RIP in the previous frame 3 Clear trace fault pending flag in fault record s process controls field before the return optional 4 Execute a return with the ret instruction Use this technique carefully a...

Page 274: ... when the fault recovery action completes No software other than the fault handling procedures is required to support this activity Three types of implicit procedure calls can be used to invoke the fault handling procedure a local call a system local call and a system supervisor call The following subsections describe actions the processor takes while handling faults It is not necessary to read th...

Page 275: ...e AC register If the processor is in user mode before execution of the return the process controls field from the fault record is not copied back to the PC register 8 8 2 System Local Fault Call When the fault handler selects an entry for a local procedure in the system procedure table entry type 102 the processor performs the same action as is described in the previous section for a local fault c...

Page 276: ...rocess controls field is copied into the PC register The mode is then switched back to user if it was in user mode before the call The processor switches back to the stack it was using when the fault occurred If the processor was in user mode when the fault occurred this operation causes a switch from the supervisor stack to the user stack If the trace fault pending flag and trace enable bits are ...

Page 277: ... and PROTECTION LENGTH faults are always precise Precise faults cannot be found in parallel records with other precise or imprecise faults 8 9 2 Imprecise Faults Faults that do not meet all of the requirements for precise faults are considered imprecise For imprecise faults the state of execution of instructions surrounding the faulting instruction may be unpredictable When instructions are execut...

Page 278: ...strict the use of pipelining to prevent imprecise faults The AC nif bit should be set if recovery from one or more imprecise faults is required For example the AC nif bit should be set if a program needs to handle and recover from unmasked integer overflow faults The fault handling procedure cannot be closely coupled with the application to perform imprecise fault recovery 8 9 5 Controlling Fault ...

Page 279: ...nstruction refers to the instruction directly after the faulting instruction or to an instruction to which the processor can logically return when resuming program execution Note that the discussions of many fault types specify that the RIP contains the address of the instruction that would have executed next had the fault not occurred Fault IP Describes the contents of the fault record s fault in...

Page 280: ...en the divisor operand of an ordinal or integer divide instruction is zero Instructions that generate this fault are RIP IP of the instruction that would have executed next if the fault had not occurred Fault IP IP of the faulting instruction Class Imprecise Program State Changes Faults may be imprecise when executing with the AC nif bit cleared INTEGER_OVERFLOW and ZERO_DIVIDE faults may not be r...

Page 281: ...egister condition code field matches the condition required by the instruction RIP No defined value Fault IP Faulting instruction Class Imprecise Program State Changes These faults may be imprecise when executing with the AC nif bit cleared No changes in the program s control flow accompany these faults A CONSTRAINT RANGE fault is generated after the FAULT cc instruction executes The program state...

Page 282: ...ed when the following conditions are present 1 the processor attempts to access an unaligned word or group of words in non MMR memory and 2 the fault is enabled by the unaligned fault mask bit in the PRCB fault configu ration word An INVALID_OPERAND fault is generated when the processor attempts to execute an instruction that has one or more operands having special requirements that are not satisf...

Page 283: ...dified For the UNALIGNED fault the memory operation completes correctly before the fault is reported In all other cases the destination is undefined Trace Reporting OPERATION UNALIGNED fault the trace is reported upon return from the OPERATION fault handler All other subtypes the trace event is lost Note OPERATION UNALIGNED fault is not implemented on i960 Kx and Sx CPUs ...

Page 284: ...ype of the additional fault detected while attempting to deliver the program fault Function The override fault handler must be accessed through a system super visor call Local and system local override fault handlers are not supported and have an unpredictable behavior Tracing is disabled upon entry into the override fault handler PC te is cleared It is restored upon return from the handler To pre...

Page 285: ...of all faults that occurred in parallel The number of parallel faults is indicated in the OSubtype Field NFP 20 See Figure 8 3 The maximum size of the fault record is implementation dependent and depends on the number of parallel and pipeline execution units in the specific implementation The parallel fault handler must be accessed through a system super visor call Local and system local parallel ...

Page 286: ...itecture protects against A PROTECTION LENGTH fault is generated when the index operand used in a calls instruction points to an entry beyond the extent of the system procedure table RIP IP of the faulting instruction Fault IP PROTECTION LENGTH IP of the faulting instruction Class PROTECTION LENGTH Is precise Program State Changes LENGTH The instruction does not execute Trace Reporting PROTECTION ...

Page 287: ...r mark It detects these events only if the TC register mode bit is set for the event If the PC register trace enable bit is also set the processor generates a fault when a trace event is detected A TRACE fault is generated following the instruction that causes a trace event or prior to the instruction for the prereturn trace event The following trace modes are available INSTRUCTION Generates a tra...

Page 288: ... trace fault with the fault subtype bit set for each subtype that occurs The prereturn trace is always reported alone When a fault type other than a TRACE fault is generated during execution of an instruction that causes a trace event the non trace fault is handled before the trace fault An exception is the prereturn trace fault which occurs before the processor detects a non trace fault and is ha...

Page 289: ...on implicit fault calls for which the fault IP field is undefined Class Precise Program State Changes All trace faults except PRERETURN are serviced after the execution of the faulting instruction The processor returns to the instruction immediately following the instruction traced in instruction issue order For PRERETURN the return is traced before it executes The processor re executes the return...

Page 290: ...te mode and BCON irp is set See Figure 13 3 Write to the first 64 bytes of on chip data RAM while the processor is in either user or supervisor mode and BCON sirp is set See Figure 13 3 Write to memory mapped registers in supervisor space from user mode Write to timer registers while in user mode when timer registers are protected against user mode writes RIP No defined value Fault IP IP of the fa...

Page 291: ...9 TRACING AND DEBUGGING ...

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Page 293: ...and fmark instructions can be used to generate trace events explicitly in the instruction stream The i960 Jx processor also provides four hardware breakpoint registers that generate trace events and trace faults Two registers are dedicated to trapping on instruction execution addresses IPB0 1 while the remaining two registers can trap on the addresses of various types of data accesses DAB0 1 9 1 T...

Page 294: ... Software can access the breakpoint event flags using modtc The processor automatically sets and clears these flags as part of its trace handling mechanism the breakpoint event flag corresponding to the trace being serviced is set in the TC while servicing a breakpoint trace fault the TC event flags are cleared upon return from the trace fault handler When the program is not in a trace fault handl...

Page 295: ... fault when a trace event is detected at the same time as another event e g non trace fault interrupt The non trace fault event is serviced before the trace fault and depending on the event type and execution mode the trace fault pending flag in the PC field of the fault record may be used to generate a fault upon return from the non trace fault event see section 9 5 2 4 Tracing on Return from Imp...

Page 296: ...n explicit call trace fault it sets the prereturn trace flag PFP register bit 3 in the new frame created by the call operation or in the current frame if a branch and link operation was performed The processor uses this flag to determine whether or not to signal a prereturn trace event on a ret instruction 9 2 4 Return Trace When the return trace mode is enabled in TC and PC te is set The processo...

Page 297: ... mark instruction It should be noted that the MARK fault subtype bit in the fault record is used to indicate a match of the instruction address breakpoint registers or the data address breakpoint registers as well as the fmark and mark instructions 9 2 7 1 Software Breakpoints mark and fmark allow breakpoint trace faults to be generated at specific points in the instruction stream When mark trace ...

Page 298: ...resources before attempting to modify these resources Rights are requested by executing the sysctl instruction as described in the following section 9 2 7 3 Requesting Modification Rights to Hardware Breakpoint Resources Application code must always first request and acquire modification rights to the hardware breakpoint resources before any attempt is made to modify them This mechanism is employe...

Page 299: ...ta address breakpoint registers If the value returned is zero the application has not gained the rights to the breakpoint resources Because the i960 Jx processor does not initialize the breakpoint registers from the control table during initialization as i960 Cx processors do the application must explicitly initialize the breakpoint registers in order to use them once modification rights have been...

Page 300: ...X No action With PC te clear breakpoints are globally disabled X 0 0 No action DABx is disabled 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Generate a Trace Fault NOTE X don t care Reserved combinations must not be used Table 9 3 Programming the Data Address Breakpoint DAB Modes DABx m1 DABx m0 Mode 0 0 Break on Data Write Access Only 0 1 Break on Data Read or Data Write Access 1 0 Break on Data Read Acce...

Page 301: ...data read access and has a value of 100FH Any of the following instructions will cause the DAB0 breakpoint to be triggered ldob 0x100f r8 ldos 0x100e r8 ld 0x100c r8 ld 0x100d r8 even unaligned accesses ldl 0x1008 r8 ldt 0x1004 r8 ldq 0x1000 r8 Note that the instruction ldt 0x1000 r8 does not cause the breakpoint to be triggered because byte 100FH is not referenced by the triple word access Data a...

Page 302: ...ction to take upon an address match Figure 9 4 Instruction Breakpoint IPB Register Format Programming the instruction breakpoint register modes is shown in Table 9 4 On the i960 Jx processor the instruction breakpoint memory mapped registers can be read by using the sysctl instruction only They can be modified by sysctl or by a word length store instruction 28 24 20 16 12 8 4 0 31 Data Address Har...

Page 303: ...ory access matching the conditions of an enabled data address breakpoint DAB register 9 4 HANDLING MULTIPLE TRACE EVENTS With the exception of a prereturn trace event which is always reported alone it is possible for a combination of trace events to be reported in the same fault record The processor may not report all events however it will always report a supervisor event and it will always signa...

Page 304: ...d This is necessary to prevent an endless loop of trace fault handling calls 9 5 1 Tracing and Interrupt Procedures When the processor invokes an interrupt handling procedure to service an interrupt it disables tracing It does this by saving the PC register s current state in the interrupt record then clearing the PC register trace enable bit On returning from the interrupt handling procedure the ...

Page 305: ...tion The trace enable bit in effect before the calls is stored in the new PFP 0 bit and is restored upon return from the routine see section 9 5 2 3 Tracing on Return from Explicit Call pg 9 15 The calls instruction and all instructions of the procedure called are traced according to the new PC te Table 9 5 summarizes all cases Table 9 5 Tracing on Explicit Call Call Type Calling Procedure Trace E...

Page 306: ...parallel override fault handler The only type of trace fault handler supported is the system supervisor type Tracing is disabled on the way to the trace fault handler Tracing is disabled by the processor on the way to an interrupt handler so an interrupt call is never traced Note that the Fault IP field of the fault record is not defined when tracing a fault call because there is no instruction po...

Page 307: ... on the target if in supervisor mode before the return and if the trace enable and trace fault pending flags are set in the PC field of the non trace fault record at FP 16 If the processor is in user mode before the return tracing is not altered The pending trace on the target instruction is lost and the return is traced according to the current PC te Table 9 7 Tracing on Return from Explicit Call...

Page 308: ...terrupt handler returns directly to the trace fault handler If the interrupt return is executed from user mode the PC register is not restored and tracing of the return occurs according to the PC te and TC modes bit fields Table 9 9 Tracing on Return from Interrupt rrr PC em PC te Tgt PC te Pending Trace on Target When Trace on Return When 111 user w w Pending Trace is Lost w TC ev 111 super w FP ...

Page 309: ...10 TIMERS ...

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Page 311: ...to the bus clock frequency or the bus clock rate divided by 2 4 or 8 The timers can be programmed to either stop when the count value reaches zero single shot mode or run continuously auto reload mode When a timer s count reaches zero the timer s interrupt unit signals the processor s interrupt controller Figure 10 1 shows a diagram of the timer functions See also Figure 10 5 for the Timer Unit st...

Page 312: ...egister TCR0 TCR1 pg 10 6 Timer Reload Register contains the timer s reload count See section 10 1 3 Timer Reload Register TRR0 TRR1 pg 10 7 For register memory locations see Table 3 5 pg 3 11 Table 10 1 Timer Performance Ranges Bus Frequency MHz Max Resolution ns Max Range mins 40 25 14 3 33 30 3 17 4 25 40 22 9 20 50 28 6 16 62 5 35 8 Table 10 2 Timer Registers Timer Unit Register Acronym Regist...

Page 313: ...unt Status TMRx tc 0 No Terminal Count 1 Terminal Count Timer Enable TMRx enable 0 Disabled 1 Enabled Timer Auto Reload Enable TMRx reload 0 Auto Reload Disabled 1 Auto Reload Enabled Timer Register Supervisor Write Control TMRx sup 0 Supervisor and User Mode Write Enabled 1 Supervisor Mode Only Write Enabled Timer Input Clock Selects TMRx csel1 0 00 1 1 Timer Clock Bus Clock 01 2 1 Timer Clock Bu...

Page 314: ... 12 2 10 1 1 2 Bit 1 Timer Enable TMRx enable The TMRx enable bit allows user software to control the timer s RUN STOP status When TMRx enable 1 The Timer Count Register TCRx value decrements every Timer Clock TCLOCK cycle TCLOCK is determined by the Timer Input Clock Select TMRx csel bits 0 1 See section 10 1 1 5 When TMRx reload 0 the timer automatically clears TMRx enable when the count reaches...

Page 315: ...uns while the processor is in Halt mode Two events can stop the timer User software explicitly clearing either TMRx enable or TMRx reload Hardware or software reset Refer to section 12 2 INITIALIZATION pg 12 2 The processor clears this bit upon hardware or software reset Refer to section 12 2 INITIALIZATION pg 12 2 10 1 1 4 Bit 3 Timer Register Supervisor Read Write Control TMRx sup The TMRx sup b...

Page 316: ...load is not set for the timer the status bit in the timer mode register TMRx tc is set and remains set until the TMRx register is accessed Figure 10 3 shows the timer count register Figure 10 3 Timer Count Register TCR0 TCR1 The valid programmable range is from 1H to FFFF FFFFH Avoid programming TCRx to 0 as it has varying results as described in section 10 5 UNCOMMON TCRX AND TRRX CONDITIONS pg 1...

Page 317: ...er TRR0 TRR1 10 2 TIMER OPERATION This section summarizes timer operation and describes load store access latency for the timer registers 10 2 1 Basic Timer Operation Each timer has a programmable enable bit in its control register TMRx enable to start and stop counting The supervisor TMRx sup bit controls write access to the enable bit This allows the programmer to prevent user mode tasks from en...

Page 318: ...ls 0 again This process repeats until software clears TMRx reload or TMR enable When TMRx reload 0 the timer stops running and sets the terminal count bit TMRx tc This bit remains set until user software reads or writes the TMRx register Either access type clears the bit The timer ignores any value specified for TMRx tc in a write request Table 10 4 Timer Mode Register Control Bit Summary Bit 3 TM...

Page 319: ...ruction activity and resource availability of processor functional units The processor ensures that the TMRx tc bit is cleared within one bus clock after a load or store instruction accesses TMRx Table 10 5 Timer Responses to Register Bit Settings Sheet 1 of 2 Name Status Action TMRx tc Terminal Count Bit 0 READ Timer clears this bit when user software accesses TMRx This bit can be set 1 bus clock...

Page 320: ...in 1 bus clock cycle after executing a read instruction from TCRx When the timer is running the pre decremented value is returned as the current value WRITE The value written to TCRx becomes the active value within 1 bus clock cycle When the timer is running the value written is decremented in the current clock cycle TRRx d31 0 Timer Reload Register READ The current TRRx count value is available w...

Page 321: ...request is still active the Interrupt Controller latches the request When a timer generates a second interrupt request before the CPU services the first interrupt request the second request may be lost When auto reload is enabled for a timer the timer continues to decrement the value in TCRx even after entry into the timer interrupt handler 10 4 POWERUP RESET INITIALIZATION Upon power up external ...

Page 322: ...mmon TMRx Control Bit Settings TRRx TCRx Bit 2 TMRx reload Bit 1 TMRx enable Action X 0 0 1 TMRx tc and TINTx set TMR enable cleared 0 0 1 1 Timer and auto reload enabled TINTx not generated and timer enable remains set 0 N 1 1 Timer and auto reload enabled TINT x set when TCRx 0 The timer remains enabled but further TINTx s are not generated N 0 1 1 Timer and auto reload enabled TINTx not set ini...

Page 323: ...ite TMRx enable 1 TMRx enable 1 TMRx reload user value TMRx sup user value TMRx csel1 0 user value TCRx Decrement Clock Unit Tick SW Write TCRx 0 and TCRx 0 TC 1 IPND tip 1 IPND tip 0 TC Detected Bus Clock SW Read SW Read Write Reload 0 Reload 1 TCRx TRRx TMRx enable 1 TC 0 TMRx enable 0 State TC 0 TMRx reload user value TMRx sup user value TMRx csel1 0 user value TMRx enable 1 TMRx enable 0 SW Wr...

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Page 325: ...11 INTERRUPTS ...

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Page 327: ...or interrupt requests may originate from external hardware sources internal timer unit sources or from software External interrupts are detected with the chip s 8 bit interrupt port and with a dedicated Non Maskable Interrupt NMI input Interrupt requests originate from software by the sysctl instruction To manage and prioritize all possible interrupts the processor integrates an on chip programmab...

Page 328: ...des a flexible low latency means for requesting and posting interrupts and minimizing the core s interrupt handling burden Acting independently from the core the interrupt controller posts interrupts requested by hardware and software sources and compares the priorities of posted interrupts with the current process priority The interrupt controller provides the following features for managing hard...

Page 329: ...d never successfully stop execution of a program of any priority In addition vector numbers 244 247 and 249 251 are reserved therefore 240 external interrupt sources and the non maskable interrupt NMI are available to the user The processor compares its current priority with the interrupt request priority to determine whether to service the interrupt immediately or to delay service The interrupt i...

Page 330: ...ed into two sections vector entries and pending interrupts Each are described in the subsections that follow Figure 11 2 Interrupt Table X X 000H 004H 020H 024H Vector 8 028H Vector 9 02CH Vector 10 3D0H Vector 243 3D4H Vector 244 3E4H Vector 248 3E8H Vector 249 3F0H Vector 251 3F4H Vector 252 400H Vector 255 Entry Type 00 Normal 10 Reserved1 01 Reserved1 Pending Priorities Pending Interrupts Entr...

Page 331: ...s two least significant bits are 0 Bits 0 and 1 of an entry indicate entry type on the i960 Jx processor only type 00 is valid The other possible entry types are reserved and must not be used 11 4 2 Pending Interrupts The pending interrupts section comprises the interrupt table s first 36 bytes divided into two fields pending priorities byte offset 0 through 3 and pending interrupts 4 through 35 E...

Page 332: ...out having to make external memory accesses The i960 Jx processor caches the following The value of the highest priority posted in the pending priorities field A predefined subset of interrupt vector numbers entries from the interrupt table Pending interrupts received from external interrupt pins This caching mechanism is non transparent the processor may modify fields in a cached interrupt table ...

Page 333: ...terrupt record is always stored on the interrupt stack adjacent to the new frame that is created for the interrupt handling procedure It includes the state of the AC and PC registers at the time the interrupt was serviced and the interrupt vector number used Relative to the new frame pointer NFP the saved AC register is located at address NFP 12 the saved PC register is located at address NFP 16 I...

Page 334: ...ts that the i960 processor family supports 3 Mixed mode five pins operate in expanded mode and can request 32 different interrupts and three pins operate in dedicated mode Dedicated mode requests are posted in the Interrupt Pending Register IPND The processor s ICU does not post expanded mode requests 11 6 2 Non Maskable Interrupt NMI The NMI pin generates an interrupt for implementation of critic...

Page 335: ...d from the interrupt table not from the internal vector cache 11 6 5 Posting Interrupts Interrupts are posted to the processor by a number of different mechanisms these are described in the following sections Software interrupts interrupts posted through the interrupt table by software running on the i960 Jx processor External Interrupts interrupts posted through the interrupt table by an external...

Page 336: ...three the following actions occur 1 The interrupt controller signals the core that a software generated interrupt is to be serviced 2 The core checks the interrupt table in memory determines the vector number of the highest priority pending interrupt and clears the pending interrupts and pending priorities bits in the table that correspond to that interrupt 3 The core detects the interrupt with th...

Page 337: ...ctions 11 6 5 4 Posting Hardware Interrupts Certain interrupts are posted directly to the processor by an implementation dependent mechanism that can bypass the interrupt table This is often done for performance reasons 11 6 6 Resolving Interrupt Priority The interrupt controller continuously compares the processor s priority to the priorities of the highest posted software interrupt and the highe...

Page 338: ...for pending interrupts in the interrupt table is made when requesting a software interrupt with sysctl or when servicing a software interrupt When a check of the interrupt table is made the algorithm shown in Example 11 4 is used Since the pending interrupts may be cached the check for pending interrupt operation may not involve any memory operations The algorithm uses synchronization because ther...

Page 339: ...ared interrupt table use sysctl periodically to guarantee recognition of pending interrupts posted in the table by the external agent Example 11 4 Sampling Pending Interrupts Check_For_Pending_Interrupts x read pending_priorities if x 0 return nothing to do y most_significant_bit x if y 31 y current_priority return x atomic_read pending_priorities synchronize if x 0 atomic_write pending_priorities...

Page 340: ...Single bits in the IPND register correspond to each of the eight dedicated external interrupt inputs or the two timer inputs to the interrupt controller The interrupt mask IMSK register selectively masks each of the dedicated mode interrupts Optionally the IMSK register can be saved and cleared when a dedicated mode interrupt is serviced This allows other hardware generated interrupts to be locked...

Page 341: ... source must remain asserted until the processor services the interrupt and explicitly clears the source External interrupt pins in expanded mode are always active low and level detect The interrupt controller ignores vector numbers 0 though 7 The output of the external priority encoders in Figure 11 6 can use the 0 vector to indicate that no external interrupts are pending The low order four bits...

Page 342: ... 1 0 GS A2 A1 A0 E1 E0 Priority Encoder 7 6 5 4 3 2 1 0 GS A2 A1 A0 E1 E0 Priority Encoder 7 6 5 4 3 2 1 0 GS A2 A1 A0 E1 E0 Priority Encoder 7 6 5 4 3 2 1 0 GS A2 A1 A0 E1 E0 Priority Encoder LSB MSB Enable Input NC Interrupt Sources up to 63 lines To i960 Jx processor s INT pins ...

Page 343: ...k Whenever an interrupt requested by XINT 7 0 or by the internal timers is serviced the IMSK register is automatically saved in register r3 of the new local register set allocated for the interrupt handler After the mask is saved the IMSK register is optionally cleared This allows all interrupts except NMIs to be masked while an interrupt is being serviced Since the IMSK register value is saved th...

Page 344: ...t inputs The i960 Jx processor provides eight external interrupt pins and one non maskable interrupt pin for detecting external interrupt requests The eight external pins can be configured as dedicated inputs where each pin is capable of requesting a single interrupt The external pins can also be configured in an expanded mode where the value asserted on the external pins represents an interrupt v...

Page 345: ...sponding pin is removed In this case the active level on the interrupt pin causes the pending bit to remain asserted After the interrupt signal is deasserted the handler then clears the interrupt pending bit for that source before return from handler is executed If the pending bit is not cleared the interrupt is re entered after the return is executed Example 11 5 demonstrates how a level detect i...

Page 346: ...nterrupt signal that is asserted for at least three CLKIN cycles for the fast sampling mode or seven CLKIN cycles for the debounce sampling mode See section 1 4 Related Documents pg 1 10 These documents have setup and hold specifications that guarantee detection of the interrupt on particular edges of CLKIN These specification are useful in designs that use synchronous logic to generate interrupt ...

Page 347: ...egister and IPND control register Table 11 1 describes the ICU registers Table 11 1 Interrupt Control Registers Memory Mapped Addresses Register Name Description Address IPND Interrupt Pending Register FF00 8500H IMSK Interrupt Mask Register FF00 8504H ICON Interrupt Control Register FF00 8510H IMAP0 Interrupt Map Register 0 FF00 8520H IMAP1 Interrupt Map Register 1 FF00 8524H IMAP2 Interrupt Map ...

Page 348: ...ed or falling edge activated Expanded mode inputs are always level detected the NMI input is always edge detected regardless of the bit s value Interrupt Mode ICON im 00 Dedicated 01 Expanded 10 Mixed 11 Reserved Signal Detection Mode ICON sdm 0 Level low activated 1 Falling edge activated Global Interrupts Enable ICON gie 0 Enabled 1 Disabled Mask Operation ICON mo 00 Move to r3 mask unchanged 01...

Page 349: ...are always detected using debounce mode Bits 15 through 31 are reserved and must be set to 0 at initialization 11 7 5 Interrupt Mapping Registers IMAP0 IMAP2 The IMAP registers Figure 11 9 are three 32 bit registers IMAP0 through IMAP2 These registers are used to program the vector number associated with the interrupt source when the source is connected to a dedicated mode input IMAP0 and IMAP1 co...

Page 350: ...l Interrupt 2 Field IMAP0 x2 External Interrupt 3 Field IMAP0 x3 28 24 20 16 12 8 4 0 External Interrupt 4 Field IMAP1 x4 x 4 4 x 4 5 x 4 6 x 4 7 x 5 4 x 5 5 x 5 6 x 5 7 x 6 4 x 6 6 x 6 7 x 7 4 x 7 5 x 7 6 x 7 7 Interrupt Map Register 1 IMAP1 External Interrupt 5 Field IMAP1 x5 External Interrupt 6 Field IMAP1 x6 External Interrupt 7 Field IMAP1 x7 28 24 20 16 12 8 4 0 Timer Interrupt 0 Field IMAP...

Page 351: ...4 0 Timer Interrupt Pending Bits IPND tip 0 No Interrupt x i p 7 x i p 6 x i p 5 x i p 4 x i p 3 x i p 2 x i p 1 x i p 0 t i p 0 t i p 1 1 Pending Interrupt External Interrupt Pending Bits IPND xip 0 No Interrupt 1 Pending Interrupt RESERVED INITIALIZE TO 0 28 24 20 16 12 8 4 0 Timer Interrupt Pending Bits IPND tip 0 No Interrupt t i p 0 t i p 1 1 Pending Interrupt 28 24 20 16 12 8 4 0 Timer Inter...

Page 352: ...imer Interrupt Mask Bits IMSK tim 0 Masked x i m 7 x i m 6 x i m 5 t i m 0 t i m 1 1 Not Masked Expanded External Interrupts Mask Bits IMSK eim 0 Masked 1 Not Masked Interrupt Mask Register IMSK Expanded Mode x i m 4 x i m 3 x i m 2 x i m 1 e i m 28 24 20 16 12 8 4 0 Timer Interrupt Mask Bits IMSK tim 0 Masked x i m 7 x i m 6 x i m 5 t i m 0 t i m 1 1 Not Masked Expanded External Interrupt Mask Bi...

Page 353: ...er before or after but not during the read modify write operation on that register This requirement ensures that modifications to IPND and IMSK take effect cleanly completely and at a well defined point Note that the processor does not assert the LOCK pin externally when executing an atomic instruction to IPND and IMSK When the processor core handles a pending interrupt it attempts to clear the bi...

Page 354: ...nterrupt controller microcode and core resources handle all stages of interrupt service Interrupt service is handled in the following stages Requesting Interrupt In the i960 Jx processor the programmable on chip interrupt controller transparently manages all interrupt requests Interrupts are generated by hardware external events or software the application program Hardware requests are signaled on...

Page 355: ...st priority posted in this table is also saved in an on chip software priority register this register is continually compared to the current process priority Servicing Interrupts If the process priority falls below that of any posted interrupt the interrupt is serviced The comparator signals the core to begin a microcode sequence to perform the interrupt context switch and branch to the first inst...

Page 356: ... Vector Processor State Software Interrupt Priority Register Internal Process Priority in PC Ack Core Vector Interrupt Core Core accepts interrupt if Processor not stopped Not executing a fault call OR Interrupt call action AND Between instruction OR At a resumption point Global Interrupt Disable Core Calls interrupt handlers Posts software interrupts Checks for software interrupts Handles all int...

Page 357: ...dling procedure is called the processor allocates a new frame on the interrupt stack and a set of local registers for the procedure If not already in supervisor mode the processor always switches to supervisor mode while an interrupt is being handled It also saves the states of the AC and PC registers for the interrupted program The interrupt procedure shares the remainder of the execution environ...

Page 358: ...g an Interrupt from Executing State When the processor receives an interrupt while in the executing state i e executing a program PC s 0 it performs the following actions to service the interrupt This procedure is the same regardless of whether the processor is in user or supervisor mode when the interrupt occurs The processor 1 Switches to the interrupt stack as shown in Figure 11 3 The interrupt...

Page 359: ... while it is servicing another interrupt and the new interrupt has a higher priority than the interrupt currently being serviced the current interrupt handler routine is interrupted Here the processor performs the same interrupt servicing action as is described in Section 11 8 3 1 to save the state of the interrupted interrupt handler routine The interrupt record is saved on the top of the interru...

Page 360: ...ins store interrupt record at FP 16 get interrupt vector number SP FP 64 IP interrupt vector number3 pending bits in interrupt table or 31 FP SP aligned to next 16 byte boundary 16 clear trace fault pending bit TC tfp clear trace enable bit TC te vector 248 NO YES continue normal operation Test for external is ICON gie 0 read pending interrupt bits clear pending interrupt bits in interrupt table i...

Page 361: ...t stack in the data cache 11 9 2 1 Vector Caching Option To reduce interrupt latency the i960 Jx processors allow some interrupt table vector entries to be cached in internal data RAM When the vector cache option is enabled and an interrupt request has a cached vector to be serviced the controller fetches the associated vector from internal RAM rather than from the interrupt table in memory Interr...

Page 362: ...umber of free frames are available to high priority interrupt service routines See section 4 2 LOCAL REGISTER CACHE pg 4 2 for more details 11 9 2 3 Caching the Interrupt Stack By locating the interrupt stack in cacheable memory the performance of interrupt returns can be improved This is because accesses to the interrupt record by the interrupt return can be satisfied by the data cache See sectio...

Page 363: ... is approximately 50 less than the 80960JA JF interrupt latency due to its core clock operating at twice the speed of CLKIN The 80960JT is approximately 70 less than the 80960JA JF and approximately 30 less than the 80960JD due to its core clock operating at three times the speed of CLKIN Table 11 3 Base Interrupt Latency Interrupt Type Detection Option Vector Caching Enabled Typical 80960JA JF La...

Page 364: ... execution of divo r15 destination divo r3 destination calls or flushreg instructions or software interrupt detection The assumptions for these tables are the same as for Table 11 8 except for instruction execution It is also assumed that the instructions are already in the cache and that tracing is disabled Table 11 4 Worst Case Interrupt Latency Controlled by divo to Destination r15 Interrupt Ty...

Page 365: ...0 N 2 3 where N is the number of bus cycles needed to perform a word load Table 11 6 Worst Case Interrupt Latency Controlled by calls Interrupt Type Detection Option Vector Caching Enabled Worst 80960JA JF Latency Bus Clocks Worst 80960JD Latency Bus Clocks Worst 80960JT 3x Latency Bus Clocks NMI Fast Yes 53 a 27 c 22 6 f Debounced Yes 56 a 32 c 26 7 f Dedicated Mode XINT 7 0 TINT 1 0 Fast Yes 58 ...

Page 366: ... 80960JT 1x Latency Bus Clocks NMI Fast Yes 96 47 31 7 2c d Debounced Yes 97 47 35 7 2c d Dedicated Mode XINT 7 0 TINT 1 0 Fast Yes 99 48 34 2c d No 107 a 53 b 34 7 3c d Debounced Yes 100 48 38 2c d No 107 a 53 b 38 7 3c d Expanded Mode XINT 7 0 TINT 1 0 Debounced Yes 96 48 38 3 2c d No 105 a 53 b 39 3 2c d NOTES a MAX 0 N 7 b MAX 0 N 3 5 c MAX 0 N 2 3 d N where N is the number of bus cycles neede...

Page 367: ...INT 1 0 Debounced Yes 88 a b 47 5 d e 34 A No 93 a b c 52 d e f 37 A k Notes a MAX 0 M 15 b MAX 0 M 28 c MAX 0 N 7 d MAX 0 M 7 5 e MAX 0 M 15 f MAX 0 n 3 5 A g h i g MAX 0 M 4 7 h MAX 0 2M 7 3 g i MAX 0 3M 13 7 g h j MAX 0 4M h 53 k MAX 0 N 7 j stq_cycles number of cycles to execute stq instruction g h i account for scoreboarding due to the possibility of long memory access latencies j and k accou...

Page 368: ... proceed to the next step of interrupt delivery Interrupt latency can be improved by avoiding the first four local registers as the destination for a Multiply Divide Unit operation Registers pfp sp and rip should be avoided for general operations as these are used for procedure linking 11 9 4 2 Masking Integer Overflow Faults for syncf The i960 core architecture requires an implicit syncf before d...

Page 369: ...12 INITIALIZATION AND SYSTEM REQUIREMENTS ...

Page 370: ......

Page 371: ...sor at initialization System data structures the processor caches several data structure pointers internally at initialization Software can reinitialize the processor When a reinitialization takes place a new PRCB and reini tialization instruction pointer are specified Reinitialization is useful for relocating data structures from ROM to RAM after initialization The i960 Jx processor supports seve...

Page 372: ... 12 1 for a flow chart of i960 Jx processor initialization Figure 12 1 Processor Initialization Flow Executing Program RESET Asserted Hardware Reset Reset State YES Assert FAIL Pin STEST Asserted On Rising Edge Of RESET Perform Internal Internal Self Test Pass NO STOP Deassert FAIL Pin Configure Registers Setup Bus Controller Assert FAIL Pin Bus Confidence Self Checksum 0 NO Deassert FAIL Pin SYSC...

Page 373: ...s in the reset state This power up reset is referred to as cold reset To ensure that all internal logic has stabilized in the reset state a valid input clock CLKIN and VCC must be present and stable for a specified time before RESET can be deasserted The processor may also be cycled through the reset state after execution has started This is referred to as warm reset For a warm reset the RESET pin...

Page 374: ...e bus confidence test passes FAIL is deasserted and the processor begins user program execution Idle Note 2 HOLD Valid Input Note 3 Notes 2 If the processor fails built in self test it will initiate one dummy load bus access 3 Since the bus is idle hold requests will be honored during reset and built in self test BE3 0 DEN BLAST Valid Output Note3 HOLDA F_XL028A V 10 000 CLKIN periods for PLL stab...

Page 375: ...Control Table offset 68H initial image in Control Table offset 68H FP g15 interrupt stack base 0xF interrupt stack base 0xF PFP r0 undefined undefined SP r1 FP 64 FP 64 RIP r2 undefined undefined IPND undefined value before software re init IMSK 00H value before software re init LMAR0 1 undefined value before software re init LMMR0 1 bit 0 0 bits 1 31 undefined bit 0 0 bits 1 31 undefined DLMCON b...

Page 376: ...le offset 14H initial image in Control Table offset 14H IMAP2 initial image in Control Table offset 18H initial image in Control Table offset 18H ICON initial image in Control Table offset 1CH initial image in Control Table offset 1CH PMCON0_1 initial image in Control Table offset 20H initial image in Control Table offset 20H PMCON2_3 initial image in Control Table offset 28H initial image in Cont...

Page 377: ...c bus failures such as external address data or control lines that are stuck shorted or open 12 2 2 3 The Fail Pin FAIL The FAIL pin signals errors in either the built in self test or bus confidence self test FAIL is asserted low for each self test Figure 12 3 When any test fails the FAIL pin remains asserted a fail code message is driven onto the address bus and the processor stops execution at t...

Page 378: ...nto the address bus and the processor stops execution at the point of failure The only way to resume normal operation of the processor is to perform a reset operation Because System Error generation can occur sometime after the BUS confidence test and even after initialization during normal processor operation the FAIL pin will be at a logic one before the detection of a System Error 12 2 2 5 FAIL...

Page 379: ...ory mapped registers or data structures Therefore to ensure complete object level compatibility portable code must not access or depend on values in this region Table 12 3 Fail Codes For BIST bit 7 1 Bit When set 6 On chip Data RAM failure detected by BIST 5 Internal Microcode ROM failure detected by BIST 4 I cache failure detected by BIST 3 D cache failure detected by BIST 2 Local register cache ...

Page 380: ... PRCB The IMI performs three functions for the processor Provides initial configuration information for the core and integrated peripherals Provides pointers to the system data structures and the first instruction to be executed after processor initialization Provides checksum words that the processor uses in its self test routine at startup Several data structures are typically included as part o...

Page 381: ...is loaded from the interrupt table and saved at location 0000 0000H of the internal data RAM The interrupt table is typically programmed in the boot ROM and then relocated to internal RAM by reinitializing the processor The fault table is typically located in boot ROM If it is necessary to locate the fault table in RAM the processor must be reinitialized The remaining data structures that an appli...

Page 382: ...s Control Table Base Address AC Register Initial Image Fault Configuration Word Interrupt Table Base Address System Procedure Table Base Address Reserved Interrupt Stack Pointer Instruction Cache Configuration Word Register Cache Control Table Interrupt Table System Procedure Table Other Architecturally Defined Data Structures Not Required As Part Of IMI Fixed Data Structures Relocatable Data Stru...

Page 383: ...orrectly The lowest order byte of each of the IBR s first 4 words are used to form the register values On the i960 Jx processor the bytes at FEFF FF30 and FEFF FF34 are not needed so the processor starts fetching at address FEFF FF38 The loading of these registers is shown in the pseudo code flow in Example 12 1 Table 12 5 Initialization Boot Record Byte Physical Address Description FEFF FF30H PMC...

Page 384: ..._cache disable D_cache invalidate D_cache BCON ctv 0 Selects PMCON14_15 to control all accesses PMCON14_15 0 Selects 8 bit bus width Exit Reset State Start_Init if STEST_ON_RISING_EDGE_OF_RESET status BIST BIST does not return if it fails FAIL_pin false PC 0x001f2002 PC Priority 31 PC em Supervisor PC te 0 PC State Interrupted ibr_ptr 0xfeffff30 ibr_ptr used to fetch IBR words Read PMCON14_15 imag...

Page 385: ...which consists of the first instruction pointer the PRCB pointer and six checksum words The PRCB pointer and the first instruction pointer are internally cached The six checksum words along with the PRCB pointer and the first instruction pointer are used in a checksum calculation which implements a confidence test of the external bus The checksum calculation is shown in the pseudo code flow in Exa...

Page 386: ...ammed in the arithmetic controls AC initial image the fault configuration word the instruction cache configuration word and the register cache configuration word Figure 12 6 shows these configuration words Table 12 6 PRCB Configuration Physical Address Description PRCB POINTER 00H Fault Table Base Address PRCB POINTER 04H Control Table Base Address PRCB POINTER 08H AC Register Initial Image PRCB P...

Page 387: ...k overflow faults No Imprecise Faults Bit AC nif 0 allow imprecise fault conditions 1 prevent imprecise fault conditions Register Cache Configuration Word Programmed Limit Disable Instruction Cache Instruction Cache Configuration Word 0 enable cache 1 disable cache Mask Non Aligned Bus Request Fault 0 enable the fault 1 mask the fault c c 0 c c 1 c c 2 o f o m n i f Initialize to 0 12 8 4 0 28 24 ...

Page 388: ...y in Data RAM Reset_block_NMI interrupt_table memory PRCB_mmr 0x10 memory 0 memory interrupt_table 248 4 4 Process System Procedure Table sysproc memory PRCB_mmr 0x14 temp memory sysproc 0xc SSP_mmr 0x3 temp SSP te 1 temp Initialize ISP FP SP and PFP ISP_mmr memory PRCB_mmr 0x1c FP 0xF ISP_mmr SP FP 64 PFP FP Initialize Instruction Cache ICCW memory PRCB_mmr 0x20 if 1 ICCW 16 disable I_cache Confi...

Page 389: ...st is issued If bit 30 is clear a fault is generated after an unaligned memory request is performed An application may elect to generate a fault to detect unwanted unaligned access Note that unaligned accesses to MMR space are not affected by bit 30 are never performed and always causes an operation unimplemented fault 12 3 2 3 Instruction Cache Configuration Word The instruction cache configurati...

Page 390: ...ed during initialization and must be completely constructed in the IMI Figure 12 7 shows the Control Table format For register bit definitions of the on chip control table registers see the following IMAP Section 11 7 5 Interrupt Mapping Registers IMAP0 IMAP2 pg 11 23 ICON Section 11 7 4 Interrupt Control Register ICON pg 11 22 PMCON Section 13 5 3 Modifying the PMCON Registers pg 13 7 TC Section ...

Page 391: ...ion PMCON2_3 Physical Memory Region 4 5 Configuration PMCON4_5 Physical Memory Region 6 7 Configuration PMCON6_7 Physical Memory Region 8 9 Configuration PMCON8_9 Physical Memory Region 10 11 Configuration PMCON10_11 Physical Memory Region 12 13 Configuration PMCON12_13 Physical Memory Region 14 15 Configuration PMCON14_15 Reserved Initialize to 0 Reserved Initialize to 0 Reserved Initialize to 0 ...

Page 392: ... processor message type See section 6 2 67 sysctl pg 6 114 for a description of sysctl The reinitialization instruction pointer and a new PRCB pointer are specified as operands to the sysctl instruction When the processor is reinitialized the fields in the newly specified PRCB are loaded as described in section 12 3 1 2 Process Control Block PRCB pg 12 16 Reinitialization is useful for relocating ...

Page 393: ...on is complete user start up code typically copies initialized data structures from ROM to RAM reinitializes the processor sets up the first stack frame changes the execution state to non interrupted and calls the _main routine This section presents an example start up routine and associated header file This simplified start up file can be used as a basis for more complete initialization routines ...

Page 394: ... char reserved_2 3 unsigned char bus_byte_3 unsigned char reserved_3 3 void first_inst unsigned prcb_ptr int check_sum 6 IBR PMCON Bus Width can be 8 16 or 32 default to 8 PMCON14_15 BOOT_BIG_ENDIAN 0 little endian 1 big endian define BUS_WIDTH bw bw 16 1 22 0 bw 32 2 22 0 define BOOT_BIG_ENDIAN on on 1 31 0 Bus configuration define DEFAULT BUS_WIDTH 8 BOOT_BIG_ENDIAN 0 define I_O BUS_WIDTH 8 BOOT...

Page 395: ...ion ROM system procedure table equ supervisor_proc 2 text align 6 or align 2 or align 4 rom_sys_proc_table space 12 Reserved word _supervisor_stack Supervisor stack pointer space 32 Preserved word _default_sysproc sysproc 0 word _default_sysproc sysproc 1 word _default_sysproc sysproc 2 word _default_sysproc sysproc 3 word _default_sysproc sysproc 4 word _default_sysproc sysproc 5 word _default_sy...

Page 396: ...x _intx _intx _intx _intx _intx _intx _intx 48 word _intx _intx _intx _intx _intx _intx _intx _intx 50 word _intx _intx _intx _intx _intx _intx _intx _intx 58 word _intx _intx _intx _intx _intx _intx _intx _intx 60 word _intx _intx _intx _intx _intx _intx _intx _intx 68 word _intx _intx _intx _intx _intx _intx _intx _intx 70 word _intx _intx _intx _intx _intx _intx _intx _intx 78 word _intx _intx ...

Page 397: ...ot needed RAM based monitor the symbol rom_data can be defined as 0 in the linker directives file lda rom_data g1 load source of copy cmpobe 0 g1 1f lda __Bdata g2 load destination lda __Edata g3 init_data ldq g1 r4 addo 16 g1 g1 stq r4 g2 addo 16 g2 g2 cmpobl g2 g3 init_data 1 Initialize the BSS area of RAM lda __Bbss g2 start of bss lda __Ebss g3 end of bss movq 0 r4 bss_fill stq r4 g2 addo 16 g...

Page 398: ...k bss _intr_stack 0x0200 6 interrupt stack bss _supervisor_stack 0x0600 6 fault supervis or stack text _fault_handler ldconst F g0 call _co ret _default_sysproc ret _intx ldconst I g0 call _co ret Example 12 5 High Level Startup Code initmain c unsigned componentid 0 main system or board specific code goes here this code is called by init s co system or board specific output routine goes here Exam...

Page 399: ...tem_init 1 falling edge activated system_init 2 falling edge activated system_init 3 falling edge activated system_init 4 level low activated system_init 5 falling edge activated system_init 6 falling edge activated system_init 7 falling edge activated mask unchanged not cached fast Physical Memory Configuration Registers DEFAULT 0 Region 0_1 DEFAULT 0 Region 2_3 DEFAULT 0 Region 4_5 I_O 0 Region ...

Page 400: ...uration is always region 14_15 since the IBR must be located there extern void start_ip extern unsigned rom_prcb extern unsigned checksum define CS_6 int checksum value calculated in linker define BOOT_CONFIG ROM const IBR init_boot_record BYTE_N 0 BOOT_CONFIG PMCON14_15 byte 1 0 0 0 reserved set to 0 BYTE_N 1 BOOT_CONFIG PMCON14_15 byte 2 0 0 0 reserved set to 0 BYTE_N 2 BOOT_CONFIG PMCON14_15 by...

Page 401: ...ile init ld Sheet 1 of 2 init ld MEMORY Enough space must be reserved in ROM after the text section to hold the initial values of the data section rom o 0xfefe0000 l 0x1fc00 rom_dat o 0xfefffc00 l 0x0300 placeholder for data image ibr o 0xfeffff30 l 0x0030 data o 0xa0000000 l 0x0300 bss o 0xa0000300 1 0x7d00 Example 12 7 Initialization Boot Record File rom_ibr c Sheet 2 of 2 ...

Page 402: ...f data section initial values ROM960 move command places the data section right after the text section _checksum _rom_prcb _start_ip HLL Rommer script embedded here the following creates a ROM image move 0 text 0 move 0 move 0 ibr 0x1ff30 mkimage 0 0 ima ihex 0 ima 0 hex mode16 map 0 quit Example 12 8 Linker Directive File init ld Sheet 2 of 2 ...

Page 403: ...file makefile LDFILE init FINALOBJ init OBJS init o ctltbl o initmain o IBR rom_ibr o LDFLAGS AJF Fcoff T LDFILE m ASFLAGS AJF V CCFLAGS AJF Fcoff V c init ima FINALOBJ rom960 LDFILE FINALOBJ init OBJS IBR gld960 LDFLAGS o OBJS s o gas960c ASFLAGS c o gcc960 CCFLAGS ...

Page 404: ...ce overshoot and undershoot 12 6 2 Power and Ground Requirements VCC VSS The large number of VSS and VCC pins effectively reduces the impedance of power and ground connections to the chip and reduces transient noise induced by current surges The i960 Jx processor is implemented in CHMOS IV technology Unlike NMOS processes power dissipation in the CHMOS process is due to capacitive charging and dis...

Page 405: ...into the VCC5 pin This resistor ensures that current drawn by the VCC5 pin does not exceed the maximum rating for this pin Figure 12 9 VCC5 Current Limiting Resistor This resistor is not necessary in systems that can guarantee the VDIFF specification 12 6 4 Power and Ground Planes Power and ground planes are recommended to be used in i960 Jx processor systems to minimize noise Justification for th...

Page 406: ... switching Place these capacitors close to the device because connection line inductance negates their effect Also for this reason the capacitors should be low inductance Chip capacitors surface mount exhibit lower inductance 12 6 6 I O Pin Characteristics The i960 Jx processor interfaces to its system through its pins This section describes the general characteristics of the input and output pins...

Page 407: ...tion to be produced internally resulting in undetermined behavior Refer to section 1 4 Related Documents pg 1 10 Specific information on input valid setup and hold times relatives to CLKIN can be found in the documents i960 Jx processor inputs which are considered asynchronous are internally synchronized to the rising edge of CLKIN Since they are internally synchronized the pins only need to be he...

Page 408: ...path delay is greater than signal rise or fall time If the line is not terminated the signal reaches its high or low level before reflections have time to dissipate and overshoot or undershoot occurs For the i960 Jx processor two termination methods are attractive AC and series An AC termination matches the impedance of the trace there by eliminating reflections due to the impedance mismatch Serie...

Page 409: ...mes shorted to VSS Intel s CMOS IV processes are immune to latchup under normal operation conditions Latchup can be triggered when the voltage limits on I O pins are exceeded causing internal PN junctions to become forward biased The following guidelines help prevent latchup Observe the maximum rating for input voltage on I O pins A C Source RS B F_CA080A A C Source B C R F_CA081A ...

Page 410: ...nce is due to electromagnetic and electrostatic fields whose effects are weaker further from the source Two types of interference must be considered in high frequency circuits electromagnetic inter ference EMI and electrostatic interference ESI EMI is caused by the magnetic field that exists around any current carrying conductor The magnetic flux from one conductor can induce current in another co...

Page 411: ...ng of two adjacent conductors The conductors act as the plates of a capacitor a charge built up on one induces the opposite charge on the other The following steps reduce ESI Separate signal lines so that capacitive coupling becomes negligible Run a ground line between two lines to cancel the electrostatic fields 1 A C B F_CA082A ...

Page 412: ......

Page 413: ...13 MEMORY CONFIGURATION ...

Page 414: ......

Page 415: ... BCU how to interpret format and control interaction of on chip data caches The physical and logical attributes for an individual location are independently programmable 13 1 1 Physical Memory Attributes The only programmable physical memory attribute for the i960 Jx microprocessor is the bus width which can be 8 16 or 32 bits wide For the purposes of assigning memory attributes the physical addre...

Page 416: ...hin a single memory subsystem For example data within one area of DRAM may be non cacheable while data in another area is cacheable Figure 13 1 shows the use of the Control Table PMCON registers with logical memory templates for a single DRAM region in a typical application Figure 13 1 PMCON and LMCON Example PMCON Registers Region 14_15 Region 12_13 Region 10_11 Region 8_9 Region 6_7 Region 4_5 R...

Page 417: ...cluding on chip data RAM The LMCON registers and their programming are described in Section 13 6 Programming the Logical Memory Attributes 13 2 Differences With Previous i960 Processors The mechanism described in this chapter is not implemented on the i960 Kx or Sx processors Although the i960 Cx processor has a memory configuration mechanism it is different from the 80960Jx s in the following way...

Page 418: ...shown in Table 13 1 Table 13 1 PMCON Address Mapping Register Control Table Entry Region Controlled PMCON0_1 0000 0000H to 0FFF FFFFH and 1000 0000H to 1FFF FFFFH PMCON2_3 2000 0000H to 2FFF FFFFH and 3000 0000H to 3FFF FFFFH PMCON4_5 4000 0000H to 4FFF FFFFH and 5000 0000H to 5FFF FFFFH PMCON6_7 6000 0000H to 6FFF FFFFH and 7000 0000H to 7FFF FFFFH PMCON8_9 8000 0000H to 8FFF FFFFH and 9000 0000H...

Page 419: ...Register Bit Description 13 4 Physical Memory Attributes at Initialization All eight PMCON registers are loaded automatically during system initialization The initial values are stored in the Control Table in the Initialization Boot Record see section 12 3 1 Initial Memory Image IMI pg 12 10 28 24 20 16 12 8 4 0 31 B W 1 B W 0 Reserved write to zero Bus Width 00 8 bit 01 16 bit 10 32 bit bus 11 re...

Page 420: ... each region Figure 13 3 Bus Control Register BCON 28 24 20 16 12 8 4 0 31 S I R Reserved write to zero Configuration Entries in Control Table Valid BCON ctv P I R P C T V 0 PMCON entries not valid default to PMCON14_15 setting 1 PMCON entries valid Internal RAM Protection BCON irp 0 Internal data RAM not protected from user mode writes Supervisor Internal RAM Protection BCON sirp 0 First 64 bytes...

Page 421: ...boundaries uses the PMCON settings of both regions Accesses that lie in the first region use that region s PMCON parameters and the remaining accesses use the second region s PMCON parameters For example an unaligned quad word load store beginning at address 1FFF FFFEH would cross boundaries from region 0_1 to 2_3 The physical parameters for region 0_1 would be used for the first 2 byte access and...

Page 422: ...A 1 6 A 1 5 A 1 4 A 1 3 A 1 2 A 3 0 Template Starting Address Data Cache Enable 0 Data caching disabled 1 Data caching enabled Byte Order read only D N Mnemonic Bit Bit Field Name Bit Position s Function A31 12 Template Starting Address 31 12 Defines upper 20 bits for the starting address fo a logical data template The lower 12 bits are fixed at zero The starting address is modulo 4 Kbytes DCEN Da...

Page 423: ... 8 M A 2 7 M A 2 6 M A 2 5 M A 2 4 M A 2 3 M A 2 2 M A 2 1 M A 2 0 M A 1 9 M A 1 8 M A 1 7 M A 1 6 M A 1 5 M A 1 4 M A 1 3 M A 1 2 Mnemonic Bit Bit Field Name Bit Position s Function MA31 12 Template Address Mask 31 12 Defines upper 20 bits for the address mask for a logical memory template The lower 12 bits are fixed at zero 0 Mask 1 Do not mask LMTE Logical Memory Template Enabled 0 Enables disa...

Page 424: ...Configuration Register DLMCON Mnemonic Bit Bit Field Name Bit Position s Function DCEN Data Cache Enable 1 Controls data caching for areas not within other logical memory templates 0 Data caching disabled 1 Write through caching enabled Instruction caching is never affected by this bit BE Big Endian Byte Order 0 Controls byte order for all accesses both instruction and data to memory 0 Little endi...

Page 425: ...match The processor will only use the logical data template when all compared address bits match Two examples help clarify the operation of the address comparators Create a template 64 Kbytes in length beginning at address 0010 0000H and ending at address 0010 FFFFH Determine the form of the candidate address to match and then program the LMADR and LMMR registers Candidate Address is of form 0010 ...

Page 426: ... Jx microprocessor supports this method by always ensuring that the DLMCON be bit is reflected in bit zero of LMADR0 and LMADR1 also labelled as LMADR be when they are read Any attempts to write bit zero of an LMADR are ignored Great care should be exercised when dynamically changing the processor s homogenous byte order See section 13 6 8 Dynamic Byte Order Changing pg 13 14 for an instruction co...

Page 427: ... LMT 13 6 6 1 Internal Memory Locations The LMT registers are not used during accesses to memory mapped registers Internal data RAM locations are never cached LMT bits controlling caching are ignored for data RAM accesses However the byte ordering of the internal data RAM is controlled by DLMCON be 13 6 6 2 Overlapping Logical Data Template Ranges Logical data templates that specify overlapping ra...

Page 428: ... use the new byte order setting This byte swapping usually results in errors because the current instruction stream uses the previous byte order setting Dynamically changing the byte order to perform limited operations is possible if the code sequence is locked in the instruction cache The application must ensure that code executes from within the locked region including faults and interrupts whil...

Page 429: ...14 EXTERNAL BUS ...

Page 430: ......

Page 431: ...rdware system allowing the processor to fetch instructions manipulate data and interact with its I O environment To perform these tasks at high bandwidth the processor features a burst transfer capability allowing up to four successive 32 bit data transfers at a maximum rate of one word every clock cycle The address data path is multiplexed for economy and bus width is programmable to 8 16 and 32 ...

Page 432: ...r of accesses per request is governed by the requested data length the programmed width of the bus and the alignment of the address 14 2 1 Basic Bus States The bus has five basic bus states idle Ti address Ta wait data Tw Td recovery Tr and hold Th During system operation the processor continuously enters and exits different bus states The bus occupies the idle Ti state when no address data transa...

Page 433: ... HOLD HOLD REQUEST ASSERTED NO HOLD HOLD REQUEST NOT ASSERTED LOCKED ATOMIC EXECUTION ATADD ATMOD IN PROGRESS NOT LOCKED NO ATOMIC EXECUTION IN PROGRESS RESET RESET ASSERTED ONCE ONCE ASSERTED Tw Td Tr Th Ti Ta READY AND BURST OR NOT READY NOT RECOVERED READY AND NO BURST HOLD AND NOT LOCKED RECOVERED AND HOLD AND NOT LOCKED HOLD NO REQUEST AND NO HOLD OR LOCKED REQUEST PENDING AND NO HOLD REQUEST...

Page 434: ...32 of these signals multiplex within the processor to serve a dual purpose During Ta the processor drives AD31 2 with the address of the bus access At all other times these lines are defined to contain data A3 2 are demultiplexed address pins providing incrementing word addresses during burst cycles AD1 0 denote burst size during Ta and data during other states The processor routinely performs dat...

Page 435: ... incrementing burst address bits Driven during Ta and Tw Td WIDTH HLT D1 0 Width and Processor Halted O Physical bus size driven during Ta and Tw Td Can denote Halt Mode D C Data Code O Data access or instruction access driven during Ta and Tw Td W R Write Read O Indication of data direction driven during Ta and Tw Td DT R Data Transmit Receive O Delayed indication of data direction driven during ...

Page 436: ...indicates whether an access is a data transaction 1 or an instruction transaction 0 The write read pin indicates the direction of data flow relative to the i960 Jx processor WIDTH1 0 D C and W R change state as needed during the Ta state DT R and DEN pins are used to control data transceivers Data transceivers may be used in a system to isolate a memory subsystem or control loading on data lines D...

Page 437: ...gs Depending on the programmed bus width the byte enable signals provide either data enables or low order address lines 8 bit region BE0 1 provide the byte address A0 A1 see Table 14 2 16 bit region BE1 provides the short word address A1 BE3 is the byte high enable signal BHE BE0 is the byte low enable signal BLE see Table 14 3 32 bit region byte enables are not encoded as address pins Byte enable...

Page 438: ...it memory they can be permanently defined this way for ease of implementation Table 14 2 8 Bit Bus Width Byte Enable Encodings Byte BE3 Not Used BE2 Not Used BE1 Used as A1 BE0 Used as A0 0 1 1 0 0 1 1 1 0 1 2 1 1 1 0 3 1 1 1 1 Table 14 3 16 Bit Bus Width Byte Enable Encodings Byte BE3 Used as BHE BE2 Not Used BE1 Used as A1 BE0 Used as BLE 0 1 0 1 0 0 2 3 0 1 1 0 0 1 1 0 0 1 0 1 0 1 2 1 1 1 0 3 0...

Page 439: ... cycle BE3 0 specify which bytes the processor uses to read the data word The processor brings W R low to denote a read operation and drives D C to the proper state For data trans ceivers DT R goes low to define the input direction During the Tw Td state the i960 Jx microprocessor deasserts ADS and asserts DEN to enable any data transceivers Since this is a non burst transaction the processor asse...

Page 440: ...n Burst Read and Write Transactions Without Wait States 32 Bit Bus CLKIN AD31 0 ALE ADS A3 2 BE3 0 WIDTH1 0 D C W R DT R DEN RDYRCV BLAST ADDR D In Invalid ADDR DATA Out 10 10 Ta Td Tr Ti Ti Ta Td Tr Ti Ti Read Idle Write Idle F_JF030A ...

Page 441: ... i960 Jx micropro cessor uses burst transactions for instruction fetching and accessing system data structures Therefore a system design incorporating an i960 Jx microprocessor must support burst transac tions Burst accesses can also result from instruction references to data types which exceed the width of the bus Maximum burst size is four data transfers independent of bus width A byte wide bus ...

Page 442: ...us Bursts Figure 14 5 16 Bit Wide Data Bus Bursts 32 Bit Burst Bus Quad Word Burst Double Word Burst Triple Word Burst Double Word Burst A3 2 00 10 11 01 16 Bit Burst Bus 4 Short Word Burst 2 Short Word Burst 2 Short Word Burst A2 1 A2 BE1 00 10 11 01 ...

Page 443: ...lways begin on an even byte boundary A0 0 see Figure 14 6 Figure 14 7 illustrates a series of bus accesses resulting from a triple word store request to 16 bit wide memory The top half of the figure shows the initial location of 12 data bytes contained in registers g4 through g6 The instruction s task is to move this data to memory at address 0AH The top half of the figure also shows the final des...

Page 444: ...th short words contents 0FEEDH and 0BA98H to address 10H 4 Non burst access to transfer the last short word contents 0FEDCH to address 14H The short word at address 16H remains unchanged Figure 14 7 Unaligned Write Transaction 1 2 3 4 5 6 7 8 F E E D F A C E F E D C B A 9 8 Registers 16 Byte Boundary G3 G4 G6 G5 G7 Memory Address A 5 6 7 8 F A C E B A 9 8 F E D C 8 C 10 14 31 0 5 6 7 8 1st Access ...

Page 445: ... and Write Transactions w o Wait States 32 bit Bus ADDR D D ADDR DATA DATA DATA DATA 1 0 1 0 CLKIN AD31 0 ALE ADS A3 2 BE3 0 WIDTH1 0 D C W R BLAST DT R DEN RDYRCV Ta Td Td Tr Ta Td Td Td Td Tr In In Out Out Out Out 00 or 01 01 or 11 00 01 10 11 ...

Page 446: ... w o Wait States 8 bit Bus ADDR D D ADDR DATA DATA DATA DATA CLKIN AD31 0 ALE ADS A3 2 BE1 A1 WIDTH1 0 D C W R BLAST DT R DEN RDYRCV Ta Td Td Tr Ta Td Td Td Td Tr 00 01 10 or 11 00 01 10 or 11 00 01 10 11 00 00 BE0 A0 In In Out Out Out Out F_JF033A 00 or 10 01 or 11 ...

Page 447: ...mples RDYRCV low on the next rising clock edge completing the transfer the state is a data state If the memory system is too slow to complete the transfer during this clock external logic drives RDYRCV high and the state is an address to data wait state Additional wait states may be inserted in similar fashion If the bus transaction is a burst the processor re enters the Tw Td state after the firs...

Page 448: ...Burst Write Transactions With 2 1 1 1 Wait States 32 bit Bus ADDR DATA 1 0 DATA DATA DATA CLKIN AD31 0 ALE ADS A3 2 BE3 0 WIDTH1 0 D C W R BLAST DT R DEN RDYRCV Ta Tw Tw Td Tw Td Tw Td Tw Td Tr Out Out Out Out F_XL032A 0 0 0 1 1 0 1 1 ...

Page 449: ...ften described as normally ready or normally not ready Normally ready logic asserts a microprocessor s input pin during all bus states except when wait states are desired Normally not ready logic deasserts a processor s input pin during all bus states except when the processor is ready The subtle nomenclature distinction is important for i960 Jx microprocessor systems because the active sense of t...

Page 450: ...ith 1 0 Wait States Extra Tr State on Read 16 Bit Bus ADDR D D ADDR DATA DATA CLKIN AD31 0 ALE ADS A3 2 BE3 BHE WIDTH1 0 D C W R BLAST DT R DEN RDYRCV Tw Td Td Tr Tr Ta Tw Td Td Tr 00 01 10 or 11 00 01 10 or 11 Ta BE0 BLE BE1 A1 01 01 0 1 0 1 Out Out In In F_XL034A ...

Page 451: ...with 1 0 Wait States Extra Tr State on Read 16 Bit Bus ADDR D D ADDR DATA DATA CLKIN AD31 0 ALE ADS A3 2 BE3 BHE WIDTH1 0 D C W R BLAST DT R DEN RDYRCV Tw Td Td Tr Tr Ta Tw Td Td Tr 00 01 10 or 11 00 01 10 or 11 Ta BE0 BLE BE1 A1 01 01 0 1 0 1 Out Out In In F_XL034A ...

Page 452: ... from a read cycle or from a Th state AD31 4 will be driven with the upper 28 bits of the read address AD3 2 will be driven identically as A3 2 the word address of the last read transfer The processor will usually drive AD1 0 with the last SIZE infor mation In cases where the core cancels a previously issued bus request AD1 0 are indeterminate 14 2 5 Data Alignment The i960 Jx microprocessor s Bus...

Page 453: ...Bytes Accesses on 8 Bit Bus WIDTH1 0 00 Accesses on 16 Bit Bus WIDTH1 0 01 Accesses on 32 Bit Bus WIDTH1 0 10 0 aligned byte access byte access byte access Table 14 7 Summary of Short Word Load and Store Accesses Address Offset from Natural Boundary in Bytes Accesses on 8 Bit Bus WIDTH1 0 00 Accesses on 16 Bit Bus WIDTH1 0 01 Accesses on 32 Bit Bus WIDTH1 0 10 0 aligned burst of 2 bytes short word...

Page 454: ...s n 1 burst s of 4 bytes byte access byte access short word access n 1 burst s of 2 short words byte access byte access short word access n 1 word access es byte access 2 n 1 2 3 4 6 n 2 3 4 10 n 3 4 14 n 3 4 burst of 2 bytes n 1 burst s of 4 bytes burst of 2 bytes short word access n 1 burst s of 2 short words short word access short word access n 1 word access es short word access 3 n 1 2 3 4 7 ...

Page 455: ...Double Word Load Store Byte Byte Accesses Short Access Aligned Short Access Aligned Byte Byte Accesses Word Access Aligned Byte Short Byte Accesses Short Short Accesses Byte Short Byte Accesses Byte Offset Word Offset F_XL028A One Double Word Burst Aligned Byte Short Word Byte Accesses Short Word Short Accesses Byte Word Short Byte Accesses Word Word Accesses Burst Aligned ...

Page 456: ...esses Word Word Word Word Word Word Word Accesses Byte Offset Word Offset One Three Word Burst Aligned Byte Short Word Word Byte Accesses Short Accesses Short Word Word Byte Word Word Short Byte Accesses Word Word Word Accesses One Four Word Burst Aligned Byte Short Word Word Word Byte Accesses Short Word Word Word Short Accesses Byte Word Word Word Short Byte Accesses F_XL029A Accesses Word Word ...

Page 457: ...us Request Misaligned One Byte From Quad Word Boundary 32 Bit Bus Little Endian Ta Td Tr Ta Td Tr Ta Td Tr Ta Td Tr CLKIN AD31 0 ALE ADS A3 2 BE3 0 WIDTH1 0 D C W R BLAST DT R DEN RDYRCV 00 00 01 10 1 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 Valid A A A D A D In In D In D In F_XL027A ...

Page 458: ...different data lines on a 32 bit bus depending upon whether address line A1 is odd or even In this example the transfer is assumed to be aligned For the word data type assume that a hexadecimal value of 0xAABBCCDD is stored in an internal processor register where 0xAA is the word s most significant byte and 0xDD is the least significant byte Table 14 9 shows how this word is transferred on the bus...

Page 459: ...bit 00 10 1st 1st CC DD CC DD DD CC DD CC 16 bit X0 1st CC DD DD CC 8 bit X0 X1 1st 2nd DD CC CC DD Table 14 11 Byte Ordering on Bus Transfers Byte Data Type Byte Data Type Bus Pins AD31 0 Bus Width Addr Bits A1 A0 Xfer Little and Big Endian 31 24 23 16 15 8 7 0 32 bit 00 01 10 11 1st 1st 1st 1st DD DD DD DD 16 bit X0 X1 1st 1st DD DD 8 bit XX 1st DD B B A A 9 9 8 8 F F E E D D C C Registers R3 R4...

Page 460: ... the 80960Jx processor asserts the LOCK pin during the first Ta of the read operation and deasserts LOCK in the last data transfer of the write operation LOCK is deasserted at the same clock edge that BLAST is asserted The i960Jx processor does not assert LOCK except while a read modify write operation is in progress While LOCK is asserted the processor can perform other non atomic accesses such a...

Page 461: ...ult bus master typically the 80960Jx that controls the bus and another that requests bus control when it performs an operation e g a DMA controller More than two bus masters may exist on the bus but this configuration requires external arbitration logic Three processor signal pins comprise the bus arbitration pin group CLKIN AD31 0 ADS W R BLAST ALE Ta Td Ti Ti Tr Ti Ta Td Tr LOCK RDYRCV Addr Inva...

Page 462: ... to assert HOLDA and float the bus on the same clock edge in which it recognizes HOLD Similarly the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD Thus bus latency is no longer than it takes the processor to finish any bus access in progress If the bus is in hold and the 80960Jx needs to regain the bus to perform a transaction the processor does not deass...

Page 463: ...A protocol with a bus status BSTAT signal In simplest terms assertion of the BSTAT output pin indicates that the CPU may soon stall unless it obtains or retains control of the bus This indication is a useful input to arbitration logic whether or not the 80960 Jx is the primary bus master The processor asserts BSTAT when one or more of the following conditions are true The bus queue in the bus cont...

Page 464: ...master As described above BSTAT will be activated for all loads and fetches but store requests do not activate BSTAT unless they fill the bus queue If the processor needs priority access to the bus to perform store operations replace store instructions with the atomic modify atmod instruction using a mask operand of all one s atmod is a read modify write instruction so the processor will assert BS...

Page 465: ...80960Jx s bus to a backplane through bus interface logic as shown in Figure 14 20 The backplane bus or system bus connects to multiple high performance I O devices often with DMA and large buffer memory for caching packets of data from disk drives or LANs Backplane buses can connect to other microprocessor local buses too creating a loosely coupled multiprocessor system for resource sharing Figure...

Page 466: ...ge interfacing to high end processors such as the Pentium R microprocessor as illustrated in Figure 14 21 In this way the i960Jx can improve the performance of complex systems such as servers by sparing the main system CPU and its local memory the task of buffering low level I O Figure 14 21 80960Jx System with 80960 Local Bus PCI Local Bus and Local Bus for High End Microprocessor i960 Jx Process...

Page 467: ... Subsystems I O subsystems vary widely according to the needs of specific applications Individual peripheral devices may be as generic as discrete logic I O ports or as specialized as an ISDN controller Typical peripherals for desktop server intelligent I O applications are Small Computer System Interface controllers supporting SCSI 1 8 bit or SCSI 2 8 16 32 bit standards For network applications ...

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Page 469: ...15 TEST FEATURES ...

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Page 471: ...ter such as an In Circuit Emulator ICE system can emulate the mounted processor and execute a test of the i960 Jx processor system 15 1 1 Entering Exiting ONCE Mode The i960 Jx processor uses the dual function LOCK ONCE pin for ONCE The LOCK ONCE pin is an input while RESET is asserted The i960 Jx processor uses this pin as an output when the ONCE mode conditions are not present ONCE mode is enter...

Page 472: ...g subsections describe the boundary scan test logic elements TAP controller Instruction register Test Data registers and TAP elements 15 2 1 1 TAP Controller The TAP controller is a 16 state machine which provides the internal control signals to the instruction register and the test data registers The state of the TAP controller is determined by the logic present on the Test Mode Select TMS pin on...

Page 473: ... the TAP pins as shown in the block diagram in Figure 15 1 The TAP is the general purpose port that provides access to the test data registers and instruction registers through the TAP controller Figure 15 1 Test Access Port Block Diagram Boundary Scan Chain ID Reg Runbist Reg TDO I R TRST TDI TMS TCK Tap Controller Bypass Reg Control And Clock Signals ...

Page 474: ...XIT1 IR PAUSE IR EXIT2 IR UPDATE IR SELECT IR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT DR SCAN 1 1 1 1 1 1 1 1 TEST LOGIC RESET RUN TEST IDLE 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOTE ALL STATE TRANSITIONS ARE BASED ON THE VALUE OF TMS TRST 1 0 ...

Page 475: ... bit is connected to TDI and the least significant bit is connected to TDO TDI is shifted into IR on each rising edge of TCK as long as TMS remains asserted When the processor enters Table 15 1 TAP Controller Pin Definitions Pin Name Mnemonic Type Definition Test Clock TCK Input Clock input for the TAP controller the instruction register and the test data registers The JTAG unit will retain its st...

Page 476: ...wing sections describe each of the test data registers See Figure 15 5 for an example of loading the data register 15 3 2 1 Device Identification Register The Device Identification register is a 32 bit register containing the manufacturer s identification code part number code and version code in the format shown in Figure 12 8 pg 12 22 The format of the register is discussed in Section 12 4 DEVIC...

Page 477: ...d on chip system logic Pins NOT in the Boundary Scan chain are power ground and JTAG pins The Boundary Scan register cells are dedicated logic and do not have any system function Data may be loaded into the Boundary Scan register master cells from the device input pins and output pin drivers in parallel by the mandatory sample preload and extest instructions Parallel loading takes place on the ris...

Page 478: ...st is selected all output signal pin values are driven by values shifted into the Boundary Scan register and may change only on the falling edge of TCK in the Update_DR state Also when extest is selected all system input pin states must be loaded into the Boundary Scan register on the rising edge of TCK in the Capture_DR state Values shifted into input latches in the Boundary Scan register are nev...

Page 479: ...ass register between TDI and TDO pins while in SHIFT_DR state effectively bypassing the processor s test logic 02 is captured in the CAPTURE_DR state This is the only instruction that accesses the Bypass register While this instruction is in effect all other test data registers have no effect on the operation of the system Test data registers with both test and system functionality perform their s...

Page 480: ...performed the result is reported in the RUNBIST register Instructions that do not call functions generate no activity in the test logic while the controller is in this state The instruction register and all test data registers retain their current state When TMS is high on the rising edge of TCK the controller moves to the Select DR Scan state 15 3 5 3 Select DR Scan State The Select DR Scan state...

Page 481: ...tes the scanning process If TMS is held low on the rising edge of TCK the controller enters the Pause DR state The instruction does not change while the TAP controller is in this state All test data registers selected by the current instruction retain their previous value during this state 15 3 5 7 Pause DR State The Pause DR state allows the test controller to temporarily halt the shifting of dat...

Page 482: ...est data registers selected by the current instruction retain their previous state In this state if TMS is held low on the rising edge of TCK the controller moves into the Capture IR state and a scan sequence for the instruction register is initiated If TMS is held high on the rising edge of TCK the controller moves to the Test Logic Reset state The instruction does not change in this state 15 3 5...

Page 483: ...struction register retains its state The controller remains in this state as long as TMS is held low When TMS goes high on the rising edges of TCK the controller moves to the Exit2 IR state 15 3 5 15 Exit2 IR State This is a temporary state If TMS is held high on the rising edge of TCK the controller enters the Update IR state which terminates the scanning process If TMS is held low on the rising ...

Page 484: ...I O 2 XINT0 I 26 ALE O 50 AD15 I O 3 XINT1 I 27 LOCK ONCE cell Enable cell1 51 AD14 I O 4 XINT2 I 28 LOCK ONCE I O 52 AD13 I O 5 XINT3 I 29 BSTAT O 53 AD12 I O 6 XINT4 I 30 BE0 O 54 AD cells Enable cell1 7 XINT5 I 31 BE1 O 55 AD11 I O 8 XINT6 I 32 BE2 O 56 AD10 I O 9 XINT7 I 33 BE3 O 57 AD9 I O 10 NMI I 34 AD31 I O 58 AD8 I O 11 FAIL I 35 AD30 I O 59 AD7 I O 12 ALE O 36 AD29 I O 60 AD6 I O 13 WIDT...

Page 485: ...ed were shifting in the TDI was being read into the Boundary Scan register This could later be written the output pins 2 4 Pass through the Exit1 DR and Update DR to continue This example does not make use of the pause states Those states would be more useful where we do not control the clock directly The pause states let the clock tick without affecting the shift registers The old instruction was...

Page 486: ...bits long d c b a 0 1 2 3 4 5 6 5 4 3 2 0 0 0 0 0 0 n n n n n P P P P P P P P P P P 1 n P RESET SELECT DR SCAN SELECT IR SCAN CAPTURE IR SHIFT IR SHIFT IR EXIT1 IR SHIFT IR SHIFT IR RESET RUN TEST IDLE c b a d b a 1 c 1 0 0 a a 1 0 b 0 0 0 1 UPDATE IR SELECT DR SCAN CAPTURE DR SHIFT DR SHIFT DR SHIFT DR SHIFT DR SHIFT DR SHIFT DR SHIFT DR SHIFT DR SHIFT DR SHIFT DR SHIFT DR SHIFT DR UPDATE DR RUN ...

Page 487: ...l output of IR Data input to TDR TDR shift register Parallel output of TDR Register selected TDO enable TDO Test Logic Reset Exit1 IR Shift IR Capture IR Select IR Scan Select DR Scan Run Test Idle Pause IR Exit2 IR Shift IR Exit1 IR Update IR Run Rest Idle INACTIVE ACTIVE INACTIVE INACTIVE ACT OLD DATA Don t care or undefined NEW INSTRUCTION IDCODE INSTRUCTION REGISTER ...

Page 488: ...93 compliant devices TCK TMS Controller State TDI Data input to IR IR shift register Parallel output of IR Data input to TDR TDR shift register Parallel output of TDR Register Selected TDO enable TDO Test Logic Reset Exit1 DR Shift DR Capture DR Select DR Scan Run Test Idle Pause DR Exit2 DR Shift DR Exit1 DR Update DR Run Rest Idle INACTIVE ACTIVE INACTIVE INACTIVE NEW DATA INSTRUCTION ID CODE TE...

Page 489: ... in bit Reserved in bit LODRVHIDRVBAR out bit FAILBAR out bit ALEBAR out bit TDO out bit WIDTH out bit_vector 1 downto 0 A32 out bit_vector 0 to 1 Reserved out bit Reserved out bit Reserved out bit Reserved out bit BLASTBAR out bit DCBAR out bit ADSBAR out bit WRBAR out bit DTRBAR out bit DENBAR out bit HOLDA out bit ALE out bit LOCKONCEBAR inout bit BSTAT out bit BEBAR out bit_vector 0 to 3 Reser...

Page 490: ...9 S09 Q09 Q10 Q11 Q12 S14 R14 Q13 S15 R15 Q14 R16 Q15 R17 Q16 P15 Q17 P16 M15 N15 CLKIN J17 RESETBAR G15 STEST F17 VCC S13 S12 S11 S10 S08 S07 S06 S05 N17 M17 M01 L17 L01 K17 K01 J01 H17 H01 G17 G01 F01 E17 A13 A11 A10 A08 A07 A06 A05 VSS R13 R12 R11 R10 R08 R07 R06 R05 N16 N02 M02 L16 L02 K16 K02 J16 J02 H16 H02 G16 G02 F02 E16 B13 B11 B10 B08 B07 B05 AVCC L15 attribute Tap_Scan_In of TDI signal ...

Page 491: ...rs identity 1 required by the standard attribute Register_Access of JX_Processor entity is Runbist 1 RUNBIST Bypass The first cell cell 0 is closest to TD0 BC_4 Input BC_1 Output3 Bidirectional attribute Boundary_Cells of JX_Processor entity is CBSC_1 BC_1 attribute Boundary_Length of JX_Processor entity is 70 attribute Boundary_Register of JX_Processor entity is 0 BC_1 STEST input X 1 BC_1 RESETB...

Page 492: ... 42 1 Z 42 BC_1 control 1 43 BC_1 ALE output3 X 51 1 Z 44 BC_1 HOLDA output3 X 52 1 Z 45 BC_1 DENBAR output3 X 51 1 Z 46 BC_1 DTRBAR output3 X 51 1 Z 47 BC_1 WRBAR output3 X 51 1 Z 48 BC_1 ADSBAR output3 X 51 1 Z 49 BC_1 DCBAR output3 X 51 1 Z 50 BC_1 BLASTBAR output3 X 51 1 Z 51 BC_1 control 1 52 BC_1 control 1 53 BC_1 A32 1 output3 X 51 1 Z 54 BC_1 A32 0 output3 X 51 1 Z 55 BC_1 WIDTH 0 output3 ...

Page 493: ...A CONSIDERATIONS FOR WRITING PORTABLE CODE ...

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Page 495: ...etc Implementation independent instruction set Procedure call mechanism Mechanism for servicing interrupts and the interrupt and process priority structure Mechanism for handling faults and the implementation independent fault types and subtypes Implementation specific features are one or all of Additions to the instruction set beyond the instructions defined by the core architecture Extensions to...

Page 496: ...of the i960 architecture A 2 3 Internal Data RAM Internal data RAM an i960 Jx processor implementation specific feature is mapped to the first 1 Kbytes of the processor s address space 0000H 03FFH The on chip data RAM may be used to cache interrupt vectors and may be protected against user and supervisor mode writes Code that relies on these special features is not directly portable to all i960 pr...

Page 497: ... data in a multiprocessor system and cacheable regions local system memory with no external hardware logic To maintain data cache coherency the i960 Jx processor implements a simple single processor coherency mechanism Also by software control the data cache can be globally enabled globally disabled or globally invalidated A data access is either Explicitly defined as cacheable or non cacheable th...

Page 498: ...ibility code should initialize reserved locations to zero When an implementation uses a reserved location the implementation specific feature is activated by a value of 1 in the reserved field Setting the reserved locations to 0 guarantees that the features are disabled A 5 INSTRUCTION SET The i960 architecture defines a comprehensive instruction set Code that uses only the architecturally defined...

Page 499: ...R SET The i960 architecture defines a way to address an extended set of 32 registers in addition to the 16 global and 16 local registers Some or all of these registers may be implemented on a specific i960 processor There are no extended registers implemented on the i960 Jx processors A 7 INITIALIZATION The i960 architecture does not define an initialization mechanism The way that an i960 based pr...

Page 500: ...960 implementations On the i960Jx processors interrupts may also be requested in software with the sysctl instruction This instruction and the software request mechanism are implementation specific Posting interrupts is also implementation specific Different implementations may optimize interrupt posting according to interrupt type and interrupt controller configuration A pending priorities and pe...

Page 501: ...mers may or may not be directly portable to other i960 processors A 10 3 Fault Implementation The architecture defines a subset of fault types and subtypes that apply to all implementations of the architecture Other fault types and subtypes may be defined by implementations to detect errant conditions that relate to implementation specific features For example the i960 Jx microprocessor provides a...

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Page 503: ...B OPCODES AND EXECUTION TIMES ...

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Page 505: ... Bits M3 M2 M1 S2 S1 T Description REG Format x x 0 x 0 src1 is a global or local register x x 1 x 0 src1 is a literal x x 0 x 1 reserved x x 1 x 1 reserved x 0 x 0 x src2 is a global or local register x 1 x 0 x src2 is a literal x 0 x 1 x reserved x 1 x 1 x reserved 0 x x x x src dst is a global or local register 1 x x x x reserved COBR Format 0 0 x src1 src2 and dst are global or local registers...

Page 506: ...8 D notor 1 0101 1000 dst src2 M3 M2 M1 1101 S2 S1 src1 58 E nand 1 0101 1000 dst src2 M3 M2 M1 1110 S2 S1 src1 58 F alterbit 1 0101 1000 dst src M3 M2 M1 1111 S2 S1 bitpos 59 0 addo 1 0101 1001 dst src2 M3 M2 M1 0000 S2 S1 src1 59 1 addi 1 0101 1001 dst src2 M3 M2 M1 0001 S2 S1 src1 59 2 subo 1 0101 1001 dst src2 M3 M2 M1 0010 S2 S1 src1 59 3 subi 1 0101 1001 dst src2 M3 M2 M1 0011 S2 S1 src1 59 ...

Page 507: ...1 1110 dst M3 M2 M1 1100 S2 S1 src 5F C movq 6 0101 1111 dst M3 M2 M1 1100 S2 S1 src 61 0 atmod 24 0110 0010 dst src2 M3 M2 M1 0000 S2 S1 src1 61 2 atadd 24 0110 0010 dst src2 M3 M2 M1 0010 S2 S1 src1 64 0 spanbit 6 0110 0100 dst M3 M2 M1 0000 S2 S1 src 64 1 scanbit 5 0110 0100 dst M3 M2 M1 0001 S2 S1 src 64 5 modac 10 0110 0100 mask dst M3 M2 M1 0101 S2 S1 mask 65 0 modify 6 0110 0101 src dst src...

Page 508: ...11 1000 dst src2 M3 M2 M1 0001 S2 S1 src1 78 2 subono 1 0111 1000 dst src2 M3 M2 M1 0010 S2 S1 src1 78 3 subino 1 0111 1000 dst src2 M3 M2 M1 0011 S2 S1 src1 78 4 selno 1 0111 1000 dst src2 M3 M2 M1 0100 S2 S1 src1 79 0 addog 1 0111 1001 dst src2 M3 M2 M1 0000 S2 S1 src1 79 1 addig 1 0111 1001 dst src2 M3 M2 M1 0001 S2 S1 src1 79 2 subog 1 0111 1001 dst src2 M3 M2 M1 0010 S2 S1 src1 79 3 subig 1 0...

Page 509: ...bine 1 0111 1101 dst src2 M3 M2 M1 0011 S2 S1 src1 7D 4 selne 1 0111 1101 dst src2 M3 M2 M1 0100 S2 S1 src1 7E 0 addole 1 0111 1110 dst src2 M3 M2 M1 0000 S2 S1 src1 7E 1 addile 1 0111 1110 dst src2 M3 M2 M1 0001 S2 S1 src1 7E 2 subole 1 0111 1110 dst src2 M3 M2 M1 0010 S2 S1 src1 7E 3 subile 1 0111 1110 dst src2 M3 M2 M1 0011 S2 S1 src1 7E 4 selle 1 0111 1110 dst src2 M3 M2 M1 0100 S2 S1 src1 7F ...

Page 510: ...2 M1 targ T S2 33 cmpobge 2 1 0011 0011 src1 src2 M1 targ T S2 34 cmpobl 2 1 0011 0100 src1 src2 M1 targ T S2 35 cmpobne 2 1 0011 0101 src1 src2 M1 targ T S2 36 cmpoble 2 1 0011 0110 src1 src2 M1 targ T S2 37 bbs 2 1 0011 0111 bitpos src M1 targ T S2 38 cmpibno 2 1 0011 1000 src1 src2 M1 targ T S2 39 cmpibg 2 1 0011 1001 src1 src2 M1 targ T S2 3A cmpibe 2 1 0011 1010 src1 src2 M1 targ T S2 3B cmpi...

Page 511: ... 1 1 0001 0110 targ T 0 17 bo 1 1 0001 0111 targ T 0 18 faultno 13 0001 1000 T 0 19 faultg 13 0001 1001 T 0 1A faulte 13 0001 1010 T 0 1B faultge 13 0001 1011 T 0 1C faultl 13 0001 1100 T 0 1D faultne 13 0001 1101 T 0 1E faultle 13 0001 1110 T 0 1F faulto 13 0001 1111 T 0 1 Indicates that it takes 1 cycle to execute the instruction plus an additional cycle to fetch the target instruction if the br...

Page 512: ...e Status Request 21 I cache Locking Status 20 Table B 7 Cycle Counts for dcctl Operations Operation Cycles to Execute Disable D cache 18 Enable D cache 18 Invalidate D cache 19 Load and Lock D cache 19 D cache Status Request 16 Quick Invalidate D cache 14 Table B 8 Cycle Counts for intctl Operations Operation Cycles to Execute Disable Interrupts 13 Enable Interrupts 13 Interrupt Status Request 8 ...

Page 513: ... opcode dst reg 1 1 0 1 00 displacement disp reg scale opcode dst 1 1 1 0 scale 00 reg displacement disp reg1 reg2 scale opcode dst reg1 1 1 1 1 scale 00 reg2 displacement Opcode Mnemonic Cycles to Execute Opcode Mnemonic Cycles to Execute 80 ldob See Note 1 9A stl See Note 1 82 stob See Note 1 A0 ldt See Note 1 84 bx 4 7 A2 stt See Note 1 85 balx 5 8 86 callx 9 12 B0 ldq See Note 1 88 ldos See No...

Page 514: ...bsolute Displacement exp MEMB 2 2 Register Indirect reg MEMB 1 1 Register Indirect with Offset exp reg MEMA 1 1 Register Indirect with Displacement exp reg MEMB 2 2 Index with Displacement exp reg scale MEMB 2 2 Register Indirect with Index reg reg scale MEMB 1 6 Register Indirect with Index Displacement exp reg reg scale MEMB 2 6 Instruction Pointer with Displacement exp IP MEMB 2 6 ...

Page 515: ...C MACHINE LEVEL INSTRUCTION FORMATS ...

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Page 517: ... begin on word boundaries MEM format instructions are encoded in one of two sub formats MEMA or MEMB MEMB supports an optional second word to hold a displacement value The following sections describe each format s instruction word fields Figure C 1 Instruction Formats 28 24 20 16 12 8 4 0 31 M M M Opcode src dst src2 Opcode src1 28 24 20 16 12 8 4 0 31 S Opcode src2 displacement T src1 28 24 20 16...

Page 518: ...truction Format pg 6 6 src1 An input to the instruction This field specifies a value or address In one case of the COBR format this field is used to specify a register in which a result is stored src2 An input to the instruction This field specifies a value or address src dst Depending on the instruction this field can be 1 an input value or address 2 the register where the result is stored or 3 b...

Page 519: ...nstructions The test if instructions also use the COBR format The COBR opcode field is eight bits two hexadecimal digits The src1 and src2 fields specify source operands for the instruction The src1 field can specify either a global or local register or a literal as determined by mode bit M1 The src2 field can only specify a global or local register Table C 4 shows the M1 src1 relationship and Tab...

Page 520: ...splacement as a signed two s complement number in the range 221 to 221 1 The processor ignores the ret instruction s displacement field C 5 MEM FORMAT The MEM format is used for instructions that require a memory address to be computed These instructions include the LOAD STORE and lda instructions Also the extended versions of the branch branch and link and call instructions bx balx and callx use ...

Page 521: ... mode along with the lda instruction allows a constant in the range 0 to 4096 to be loaded into a register Table C 6 Addressing Modes for MEM Format Instructions Format MODE Addressing Mode Address Computation of Instr Words MEMA 00 Absolute Offset offset 1 10 Register Indirect with Offset abase offset 1 MEMB 0100 Register Indirect abase 1 0101 IP with Displacement IP displacement 8 2 0110 Reserve...

Page 522: ...rocessor automati cally scales the index register value by the amount specified in the SCALE field Table C 7 gives the encoding of the scale field The optional displacement field is contained in the word following the instruction word The displacement is a 32 bit signed two s complement value For the IP with displacement mode the value of the displacement field plus eight is added to the address o...

Page 523: ...D REGISTER AND DATA STRUCTURES ...

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Page 525: ...ol Register pg 9 7 D 10 D 10 DAB Data Address Breakpoint Register Format Section 9 2 7 5 Data Address Breakpoint DAB Registers pg 9 9 D 11 D 11 IPB Instruction Breakpoint Register Format Section 9 2 7 6 Instruction Breakpoint IPB Registers pg 9 10 D 11 D 12 TMR0 1 Timer Mode Register Section 10 1 1 Timer Mode Registers TMR0 TMR1 pg 10 3 D 12 D 13 TCR0 1 Timer Count Register Section 10 1 2 Timer Co...

Page 526: ... PMCON Registers pg 13 4 D 23 D 26 BCON Bus Control Register Section 13 4 1 Bus Control BCON Register pg 13 6 D 24 D 27 DLMCON Default Logical Memory Configu ration Register Section 13 6 Programming the Logical Memory Attributes pg 13 8 D 24 D 28 LMADR0 1 Logical Memory Template Starting Address Registers Section 13 6 Programming the Logical Memory Attributes pg 13 8 D 25 D 29 LMMR0 1 Logical Memo...

Page 527: ...ontrols AC Register pg 3 18 28 24 20 16 12 8 4 0 31 Condition Code Bits AC cc Integer Overflow Flag AC of 0 No Overflow 1 Overflow Integer Overflow Mask Bit AC om 0 No Mask 1 Mask No Imprecise Faults Bit AC nif 0 Some Faults are Imprecise 1 All Faults are Precise Reserved Initialize to 0 c c 0 c c 1 c c 2 o m n i f o f ...

Page 528: ...1 Trace Enable Bit PC te 0 Globally disable trace faults 1 Globally enable trace faults Execution Mode Flag PC em 0 user mode 1 supervisor mode Trace Fault Pending PC tfp 0 no fault pending 1 fault pending State Flag PC s 0 executing 1 interrupted Priority Field PC p 0 31 process priority Reserved t e t s p p p p p 4 3 2 1 0 f m e p Do not modify ...

Page 529: ...ea Procedure Stack Previous Frame Pointer PFP Stack Pointer SP Return Instruction Pointer RIP user allocated stack unused stack stack growth toward higher addresses padding area user allocated stack Current Register Set Previous Frame Pointer PFP Stack Pointer SP reserved for RIP Frame Pointer FP Previous Stack Frame Current Stack Frame g0 g15 r0 r1 r2 r15 r0 r1 r2 r15 ...

Page 530: ...Table pg 7 15 Reserved Initialize to 0 000H 008H 00CH 010H 02CH 034H 030H 038H 03CH 438H 43CH Entry Type 00 Local 10 Supervisor Trace Control Bit 0 31 Procedure Entry T supervisor stack pointer base procedure entry 2 procedure entry 1 procedure entry 0 procedure entry 259 Preserved address 0 31 1 2 ...

Page 531: ... Figure D 5 PFP Previous Frame Pointer Register r0 Section 7 8 RETURNS pg 7 20 28 24 20 16 12 8 4 0 31 Return Status a 4 p r t 2 r t 1 r t 0 Return Type Field PFP rt Pre Return Trace Flag PFP p Previous Frame Pointer Address PFP a a 3 1 ...

Page 532: ...ntry CONSTRAINT Fault Entry ARITHMETIC Fault Entry OPERATION Fault Entry TRACE Fault Entry PARALLEL OVERRIDE Fault Entry Local Call Entry Fault Handler Procedure Address System Call Entry Fault Handler Procedure Number 0000 027FH n n 4 n n 4 0 1 2 0 0 1 00H 08H 10H 18H 20H 28H 30H 38H 40H 48H 50H FCH Reserved Initialize to 0 0 31 31 Fault Table 0 1 2 ...

Page 533: ... 16 NFP 12 NFP 8 NFP 4 OTYPE OSUBTYPE ARITHMETIC CONTROLS FTYPE n FSUBTYPE n OVERRIDE FAULT DATA FAULT DATA NFP n 1 32 NFP 24 n 32 NFP 20 n 32 NFP 12 n 32 NFP 8 n 32 NFP 4 n 32 NFP 64 NFP 52 NFP 48 NFP 44 NFP 32 FTYPE 1 FSUBTYPE 1 ADDRESS OF FAULTING INSTRUCTION 1 28 24 20 16 12 8 4 0 31 RESUMPTION INFORMATION FAULT DATA n means number of faults NOTES NFP means New Frame Pointer ...

Page 534: ... b Call Trace Mode TC c Pre Return Trace Mode TC p Supervisor Trace Mode TC s Mark Trace Mode TC mk Return Trace Mode TC r i b c r p s m k Reserved Hardware Breakpoint Event Flags Instruction Address Breakpoint 0 TC i0f Instruction Address Breakpoint 1 TC i1f Data Address Breakpoint 0 TC d0f Data Address Breakpoint 1 TC d1f i 0 f i 1 f d 0 f d 1 f 28 24 20 16 12 8 4 0 31 DAB0 e e 1 0 m 0 m 1 e 0 e...

Page 535: ...9 9 Figure D 11 IPB Instruction Breakpoint Register Format Section 9 2 7 6 Instruction Breakpoint IPB Registers pg 9 10 28 24 20 16 12 8 4 0 31 Data Address Hardware Reset Value 0000 0000H Software Re init Value 0000 0000H 28 24 20 16 12 8 4 0 31 IPBx Mode Instruction Address m 1 m 0 Hardware Reset Value 0000 0000H Software Re init Value 0000 0000H ...

Page 536: ...ed 1 Enabled Timer Auto Reload Enable TMRx reload 0 Auto Reload Disabled 1 Auto Reload Enabled Timer Register Supervisor Write Control TMRx sup 0 Supervisor and User Mode Write Enabled 1 Supervisor Mode Only Write Enabled Timer Input Clock Selects TMRx csel1 0 00 1 1 Timer Clock Bus Clock 01 2 1 Timer Clock Bus Clock 2 10 4 1 Timer Clock Bus Clock 4 16 12 8 11 8 1 Timer Clock Bus Clock 8 Reserved ...

Page 537: ... DATA STRUCTURES D 13 D Figure D 14 TRR0 1 Timer Reload Register Section 10 1 3 Timer Reload Register TRR0 TRR1 pg 10 7 Timer Reload Register TRR0 TRR1 28 24 20 4 0 16 12 8 Timer Auto Reload Value TRRx d31 0 D31 0 ...

Page 538: ...ctor 248 3E8H Vector 249 3F0H Vector 251 3F4H Vector 252 400H Vector 255 Entry Type 00 Normal 10 Reserved1 01 Reserved1 Pending Priorities Pending Interrupts Entry 8 Entry 9 NMI Vector Vector Entry Instruction Pointer Reserved Initialize to 0 Preserved 0 0 1 2 7 8 31 Entry 252 Entry 255 Entry 243 Entry 10 3E0H Vector 247 11 Reserved1 1 Vector entries with a reserved type cause unpredictable behavi...

Page 539: ...TACK AND INTERRUPT RECORD pg 11 7 Padding Area Saved Arithmetic Controls Register New Frame NFP 8 NFP 16 NFP 12 NFP Current Frame FP Saved Process Controls Register Interrupt Stack 0 31 Current Stack 0 31 Local Supervisor or Interrupt Stack Vector Number Reserved Stack Growth Interrupt Record Optional Data not used by 80960Jx ...

Page 540: ...d Mask Operation ICON mo 00 Move to r3 mask unchanged 01 Move to r3 and clear for dedicated mode interrupts 10 Move to r3 and clear for expanded mode interrupts 11 Move to r3 and clear for dedicated and expanded Vector Cache Enable ICON vce 0 Fetch from external memory 1 Fetch from internal RAM Sampling Mode ICON sm 0 debounce 1 fast Reserved Initialize to 0 Interrupt Control Register ICON 28 24 2...

Page 541: ...xternal Interrupt 1 Field IMAP0 x1 External Interrupt 2 Field IMAP0 x2 External Interrupt 3 Field IMAP0 x3 28 24 20 16 12 8 4 0 External Interrupt 4 Field IMAP1 x4 x 4 4 x 4 5 x 4 6 x 4 7 x 5 4 x 5 5 x 5 6 x 5 7 x 6 4 x 6 6 x 6 7 x 7 4 x 7 5 x 7 6 x 7 7 Interrupt Map Register 1 IMAP1 External Interrupt 5 Field IMAP1 x5 External Interrupt 6 Field IMAP1 x6 External Interrupt 7 Field IMAP1 x7 28 24 2...

Page 542: ... i m 1 x i m 0 28 24 20 16 12 8 4 0 Timer Interrupt Mask Bits IMSK tim 0 Masked x i m 7 x i m 6 x i m 5 t i m 0 t i m 1 1 Not Masked Expanded External Interrupts Mask Bits IMSK eim 0 Masked 1 Not Masked Interrupt Mask Register IMSK Expanded Mode x i m 4 x i m 3 x i m 2 x i m 1 e i m 28 24 20 16 12 8 4 0 Timer Interrupt Mask Bits IMSK tim 0 Masked x i m 7 x i m 6 x i m 5 t i m 0 t i m 1 1 Not Maske...

Page 543: ...xternal Interrupt Pending Bits IPND xip 0 No Interrupt 1 Pending Interrupt RESERVED INITIALIZE TO 0 28 24 20 16 12 8 4 0 Timer Interrupt Pending Bits IPND tip 0 No Interrupt t i p 0 t i p 1 1 Pending Interrupt 28 24 20 16 12 8 4 0 Timer Interrupt Pending Bits IPND tip 0 No Interrupt x i p 7 x i p 6 t i p 0 t i p 1 1 Pending Interrupt External Interrupt Pending Bits IPND xip 0 No Interrupt 1 Pendin...

Page 544: ...t Table Base Address Control Table Base Address AC Register Initial Image Fault Configuration Word Interrupt Table Base Address System Procedure Table Base Address Reserved Interrupt Stack Pointer Instruction Cache Configuration Word Register Cache Control Table Interrupt Table System Procedure Table Other Architecturally Defined Data Structures Not Required As Part Of IMI Fixed Data Structures Re...

Page 545: ...verflow faults 1 mask overflow faults No Imprecise Faults Bit AC nif 0 allow imprecise fault conditions 1 prevent imprecise fault conditions Register Cache Configuration Word Programmed Limit Disable Instruction Cache Instruction Cache Configuration Word 0 enable cache 1 disable cache Mask Non Aligned Bus Request Fault 0 enable the fault 1 mask the fault c c 0 c c 1 c c 2 o f o m n i f Initialize ...

Page 546: ...3 Configuration PMCON2_3 Physical Memory Region 4 5 Configuration PMCON4_5 Physical Memory Region 6 7 Configuration PMCON6_7 Physical Memory Region 8 9 Configuration PMCON8_9 Physical Memory Region 10 11 Configuration PMCON10_11 Physical Memory Region 12 13 Configuration PMCON12_13 Physical Memory Region 14 15 Configuration PMCON14_15 Reserved Initialize to 0 Reserved Initialize to 0 Reserved Init...

Page 547: ...ET pg 12 22 Figure D 25 PMCON Register Bit Description Section 13 1 1 Physical Memory Attributes pg 13 1 28 24 20 4 0 16 12 8 1 1 0 0 1 0 0 0 0 0 0 0 Manufacturer ID Part Number Version Model Gen Product Type 28 24 20 16 12 8 4 0 31 B W 1 B W 0 Reserved write to zero Bus Width 00 8 bit 01 16 bit 10 32 bit bus 11 reserved do not use ...

Page 548: ... P I R P C T V 0 PMCON entries not valid use PMCON15 setting 1 PMCON entries valid Internal RAM Protection BCON irp 0 Internal data RAM not protected from user mode writes Supervisor Internal RAM Protection BCON sirp 0 First 64 bytes not protected from supervisor mode writes 1 First 64 bytes protected from supervisor mode writes 1 Internal data RAM protected from user mode writes 28 24 20 16 12 8 ...

Page 549: ... A 2 8 A 2 7 A 2 6 A 2 5 A 2 4 A 2 3 A 2 2 A 2 1 A 2 0 A 1 9 A 1 8 A 1 7 A 1 6 A 1 5 A 1 4 A 1 3 A 1 2 A 3 0 Template Starting Address Data Cache Enable 0 Data caching disabled 1 Data caching enabled Byte Order read only D N 0 Little endian 1 Big endian Reserved 28 24 20 16 12 8 4 0 31 write to zero Logical Memory Template Enabled 0 LMT disabled 1 LMT enabled Template Address Mask L M T E M A 3 1 ...

Page 550: ......

Page 551: ...GLOSSARY ...

Page 552: ......

Page 553: ...hronous fault occurs the address of the faulting instruction in the fault record and the saved IP are undefined i960 core architecture does not define any fault types that are asynchronous Big Endian The bus controller reads or writes a data word s least significant byte to the bus eight most significant data lines D31 24 Big endian systems store the least significant byte at the highest byte addr...

Page 554: ...ccesses to predefined address regions or warn the user program if accesses occur Hardware Reset The assertion of the RESET pin equivalent to powerup IBR See Initialization Boot Record IMI See Initial Memory Image Imprecise Faults Faults that are allowed to be generated out of order from where they occur in the instruction stream When an imprecise fault is generated the processor indicates the addr...

Page 555: ...en it executes interrupt handling procedures Interrupt Table A data structure that contains vectors to interrupt handling procedures and fields for storing pending interrupts When the processor receives an interrupt it uses the vector number that accompanies the interrupt to locate an interrupt vector in the interrupt table The interrupt table s pending interrupt fields contain bits that indicate ...

Page 556: ...ord etc on a data cache miss Exceptions are byte and short word accesses which are always promoted to words No Imprecise Faults NIF Bit AC register bit 15 This flag determines whether or not imprecise faults are allowed to occur If set all faults are required to be precise if clear certain faults can be imprecise Non Maskable Interrupt NMI Provides an interrupt that cannot be masked and has a high...

Page 557: ...cellaneous pieces of information used to control processor activity and show current processor state Flags and fields in this register include the trace enable bit execution mode flag trace fault pending flag state flag priority field and internal state field All unused bits in this register are reserved and must be set to 0 Register Score boarding Internal flags that indicate a particular registe...

Page 558: ...k A contiguous array of bytes in the address space that grows from low addresses to high addresses It consists of contiguous frames one frame for each active procedure i960 architecture defines three stacks local supervisor and interrupt State Flag PC register bit 10 This flag indicates to software that the processor is currently executing a program 0 or servicing an interrupt 1 State The type of ...

Page 559: ...ructure as the system procedure table Trace Control Bit Bit 0 of byte 12 of the system procedure table This bit specifies the new value of the trace enable bit when a supervisor call causes a switch from user mode to supervisor mode Setting this bit to 1 enables tracing setting it to 0 disables tracing Trace Controls TC Register A 32 bit register that controls processor tracing facilities This reg...

Page 560: ...e event and its location in the instruction stream User Mode One of two execution modes user and supervisor that the processor can be in When the processor is in user mode it uses the local stack and is not allowed to use the modpc instruction or any other implementation defined instruction that is designed to be used only in supervisor mode Vector Number The number of an entry in the interrupt ta...

Page 561: ...INDEX ...

Page 562: ......

Page 563: ...ignment registers and literals 3 4 alterbit 6 12 and 6 13 andnot 6 13 architecture reserved memory space 12 9 argument list 7 13 Arithmetic Controls AC Register 3 18 Arithmetic Controls AC register 3 18 condition code flags 3 19 initial image 12 19 initialization 3 18 integer overflow flag 3 20 integer overflow mask bit 3 20 no imprecise faults bit 3 20 arithmetic instructions 5 7 add subtract mul...

Page 564: ...om 7 21 branch and link instruction 7 1 branch if greater or equal instruction 3 20 breakpoint registers A 7 resource request message 9 7 Breakpoint Control BPCON register 9 8 D 10 programming 9 8 Breakpoint Control Register BPCON 9 8 bswap 6 23 built in self test 12 2 bus confidence self test 12 6 Bus Control BCON register 13 6 BCON irp bit 4 2 BCON sirp bit 4 1 Bus Control Unit BCU 14 22 changin...

Page 565: ...nd stack management 7 4 frame pointer 7 4 previous frame pointer 7 5 return type field 7 5 stack pointer 7 4 stack frame 7 2 call and return operations 7 5 call operation 7 6 return operation 7 7 calls 3 24 6 25 7 2 7 6 call trace mode 9 3 callx 6 27 7 2 7 6 carry conditions 3 19 check bit instruction 6 29 chkbit 6 29 clear bit instruction 6 30 clock input CLKIN 12 34 clrbit 6 30 cmpdeci 6 31 cmpd...

Page 566: ...ral units A 7 data movement instructions 5 5 load address instruction 5 6 load instructions 5 5 move instructions 5 6 data RAM 3 16 Data Register timing diagram 15 18 data structures control table 3 1 3 7 3 12 fault table 3 1 3 12 Initialization Boot Record IBR 3 1 3 11 interrupt stack 3 1 3 12 interrupt table 3 1 3 12 literals 3 4 local stack 3 1 Process Control Block PRCB 3 1 3 11 supervisor sta...

Page 567: ... 9 procedure invocation 8 6 return instruction pointer RIP 8 14 stack usage 8 6 supervisor stack 8 2 system procedure table 8 2 system local calls 8 2 system supervisor calls 8 2 user stack 8 2 fault record 8 6 address of faulting instruction field 8 7 fault subtype field 8 7 location 8 6 8 8 structure 8 7 fault table 3 1 3 12 8 4 alignment 3 15 local call entry 8 6 location 8 4 system call entry ...

Page 568: ... 12 23 hardware requirements 12 34 MON960 12 23 power and ground 12 34 software 6 114 Initialization Boot Record IBR 3 1 3 11 12 1 12 13 12 15 alignment 3 15 initialization data structures 3 11 initialization mechanism A 5 initialization requirements architecture reserved memory space 12 9 control table 12 21 D 22 data structures 12 10 Process Control Block 12 16 Instruction Breakpoint IBP registe...

Page 569: ...mpibg 6 35 cmpibge 6 35 cmpibl 6 35 cmpible 6 35 cmpibne 6 35 cmpibno 6 35 cmpibo 6 35 cmpinci 6 32 cmpinco 6 32 cmpis 5 12 cmpo 5 12 6 33 cmpobe 6 35 cmpobg 6 35 cmpobge 6 35 cmpobl 6 35 cmpoble 6 35 cmpobne 6 35 concmpi 6 38 concmpo 6 38 dcctl 3 23 4 6 4 10 6 40 divi 6 47 divo 6 47 ediv 6 48 emul 6 49 eshro 6 50 extract 6 51 faulte 6 52 faultg 6 52 faultge 6 52 faultl 6 52 faultle 6 52 faultne 6...

Page 570: ...6 100 shrdi 6 100 shri 6 100 shro 6 100 spanbit 6 103 st 2 2 3 15 6 104 stib 2 2 6 104 stis 2 2 6 104 stl 3 15 4 7 6 104 stob 2 2 6 104 stos 2 2 stq 3 16 4 7 6 104 stt 4 7 6 104 subc 6 108 subi 6 112 subie 6 109 subig 6 109 subige 6 109 subil 6 109 subile 6 109 subine 6 109 subino 6 109 subio 6 109 subo 6 112 suboe 6 109 subog 6 109 suboge 6 109 subol 6 109 subole 6 109 subone 6 109 subono 6 109 s...

Page 571: ...P0 IMAP2 registers 11 23 interrupt mask saving 11 17 Interrupt Mask IMSK register 1 5 11 25 D 18 Interrupt Mask IMSK Registers 11 26 Interrupt Pending IPND Register 11 25 Interrupt Pending IPND register 1 5 11 25 atomic read modify write sequence 3 6 interrupt performance caching of interrupt handling 11 36 interrupt stack 11 36 local register cache 11 36 interrupt pins dedicated mode 11 8 expande...

Page 572: ... 3 1 3 4 addressing 3 4 little endian byte order 2 4 3 16 LMADR register LMCON registers load address instruction 6 73 load instructions 5 5 6 70 load and lock mechanism 4 5 local calls 7 2 7 14 8 2 call 7 2 callx 7 2 local register cache 7 3 overview 1 5 3 17 4 2 local registers 3 1 7 2 allocation 3 3 7 2 management 3 3 overview 1 9 usage 7 2 local stack 3 1 logical data templates effective range...

Page 573: ...movt 6 81 muli 6 84 mulo 6 84 multiple fault conditions 8 9 multiply integer instruction 6 84 multiply ordinal instruction 6 84 N nand 6 85 NMI see Non Maskable Interrupt NMI No Imprecise Faults AC nif bit 8 15 8 20 Non Maskable Interrupt NMI 11 3 11 8 signal 11 18 nor 6 86 not 6 87 notand 6 87 notbit 6 88 notor 6 89 O On Circuit Emulation ONCE mode 12 1 15 1 OPERATION UNIMPLEMENTED 4 1 or 6 90 or...

Page 574: ...region boundaries bus transactions across 13 7 register access 11 27 addressing 3 4 addressing and alignment 3 5 Breakpoint Control BPCON 9 7 cache 3 17 4 2 control 3 7 memory mapped 3 6 DEVICEID memory location 3 3 global 3 2 indirect addressing mode register indirect with displacement 2 7 register indirect with index 2 7 register indirect with index and displacemen t 2 8 register indirect with o...

Page 575: ...errupt mask 11 17 scanbit 6 95 scanbyte 6 96 sele 5 6 6 97 select based on equal instruction 5 6 select based on less or equal instruction 5 6 select based on not equal instruction 5 6 select based on ordered instruction 5 6 Select Based on Unordered 5 6 select instructions 6 120 self test STEST pin 12 6 selg 5 6 6 97 selge 5 6 6 97 sell 5 6 6 97 selle 5 6 6 97 selne 5 6 6 97 selno 5 6 6 97 selo 5...

Page 576: ... 15 2 architecture 15 3 Asynchronous Reset Input TRST pin 15 5 block diagram 15 3 Serial Test Data Output TDO pin 15 5 state diagram 15 4 Test Clock TCK pin 15 5 Test Mode Select TMS pin 15 5 test features 15 2 test instructions 6 118 Test Mode Select TMS line 15 2 teste 6 118 testg 6 118 testge 6 118 testl 6 118 testle 6 118 testne 6 118 testno 6 118 testo 6 118 32 bit bus width byte enable encod...

Page 577: ...rite transaction 14 14 U unordered numbers 3 19 user space family registers and tables 3 11 user stack 3 12 7 19 alignment 3 15 user supervisor protection model 3 23 supervisor mode resources 3 23 usage 3 24 V vector entries 11 5 NMI 11 5 structure 11 5 W warm reset 11 28 12 3 words triple and quad 2 3 X XINT see external interrupt XINT signals 11 18 xnor 6 120 xor 6 120 ...

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