Intel i960 Jx, Developer'S Manual, Page: 316 / 578

TIMERS
10-6
10.1.1.5 Bits 4, 5 - Timer Input Clock Select (TMRx.csel1:0)
User software programs the TMRx.csel bits to select the Timer Clock (TCLOCK) frequency. See
Table 10-3 . As shown in Figure 10-1 , the bus clock is an input to the timer clock unit. These bits
allow the application to specify whether TCLOCK runs at or slower than the bus clock frequency.
The processor clears these bits upon hardware or software reset (TCLOCK = Bus Clock).
10.1.2 Timer Count Register (TCR0, TCR1)
The Timer Count Register (TCRx) is a 32-bit register that contains the timer’s current count. The
register value decrements with each timer clock tick. When this register value decrements to zero
(terminal count), a timer interrupt is generated. When TMRx.reload is not set for the timer, the
status bit in the timer mode register (TMRx.tc) is set and remains set until the TMRx register is
accessed.
Figure 10-3 shows the timer count register.
Figure 10-3. Timer Count Register (TCR0, TCR1)
The valid programmable range is from 1H to FFFF FFFFH. (Avoid programming TCRx to 0 as it
has varying results as described in
section 10.5, “UNCOMMON TCRX AND TRRX
CONDITIONS” (pg. 10-12) .)
User software can read or write TCRx whether the timer is running or stopped. Bit 3 of TMRx
determines user read/write control (see
section 10.1.1.4 ). The TCRx value is undefined after
hardware or software reset.
Table 10-3. Timer Input Clock (TCLOCK) Frequency Selection
Bit 5
TMRx.csel1
Bit 4
TMRx.csel0
Timer Clock (TCLOCK)
0 0 Timer Clock = Bus Clock
0 1 Timer Clock = Bus Clock / 2
1 0 Timer Clock = Bus Clock / 4
1 1 Timer Clock = Bus Clock / 8
28 24 20 4 0 16 12 8
Timer Count Register (TCR0, TCR1)
Timer Count Value - TCRx.d31:0
D31:0