Intel i960 Jx, Developer'S Manual

Page: 329 / 578

INTERRUPTS
11-3
11
11.2 SOFTWARE REQUIREMENTS FOR INTERRUPT HANDLING
To use the processor’s interrupt handling facilities, user software must provide the following items
in memory:
• Interrupt Table
• Interrupt Handler Routines
• Interrupt Stack
These items are established in memory as part of the initialization procedure. Once these items are
present in memory and pointers to them have been entered in the appropriate system data
structures, the processor handles interrupts automatically and independently from software.
11.3 INTERRUPT PRIORITY
Each interrupt vector number is eight bits in length, allowing up to 256 unique vector numbers to be
defined in principle. Each vector number priority is defined by dividing the vector number by eight.
Thus, at each priority level, there are eight possible vector numbers (e.g., vector numbers 8-15 have a
priority of 1 and vector numbers 246-255 have a priority of 31). Vector numbers 0-7 cannot be used
because a priority-0 interrupt would never successfully stop execution of a program of any priority. In
addition, vector numbers 244-247 and 249-251 are reserved; therefore, 240 external interrupt sources
and the non-maskable interrupt (NMI) are available to the user.
The processor compares its current priority with the interrupt request priority to determine whether
to service the interrupt immediately or to delay service. The interrupt is serviced immediately if its
priority is higher than the priority of the program or interrupt the processor is executing currently.
If the interrupt priority is less than or equal to the processor’s current priority, the processor does
not service the request but rather posts it as a pending interrupt. See
section 11.4.2, “Pending
Interrupts” (pg. 11-5) . When multiple interrupt requests are pending at the same priority level, the
request with the highest vector number is serviced first.
Priority-31 interrupts are handled as a special case. Even when the processor is executing at priority
level 31, a priority-31 interrupt interrupts the processor. On the i960 Jx processor, the non-maskable
interrupt (NMI) interrupts priority-31 execution; no interrupt can interrupt an NMI handler.