Intel Embedded Intel486, Hardware Reference Manual

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4-27
BUS OPERATION
4.3.4.2 Burst and Cache Line Fill Order
The burst order used by the Intel486 processor is shown in Table 4-8 . This burst order is followed
by any burst cycle (cache or not), cache line fill (burst or not) or code prefetch.
The Intel486 processor presents each request for data in an order determined by the first address
in the transfer. For example, if the first address was 104 the next three addresses in the burst will
be 100, 10C and 108. An example of burst address sequencing is shown in
Figure 4-18 .
Figure 4-18. Burst Cycle Showing Order of Addresses
The sequences shown in Table 4-8 accommodate systems with 64-bit buses as well as systems
with 32-bit data buses. The sequence applies to all bursts, regardless of whether the purpose of
the burst is to fill a cache line, perform a 64-bit read, or perform a pre-fetch. If either BS8# or
BS16# is asserted, the Intel486 processor completes the transfer of the current 32-bit word before
Table 4-8. Burst Order (Both Read and Write Bursts)
First Address Second Address Third Address Fourth Address
0 4 8 C
4 0 C 8
8 C 0 4
C 8 4 0
242202-039
CLK
ADS#
A31–A2
RDY#
BLAST#
DATA
Ti
To Processor
T1 T2 T2 T2 T2 Ti
KEN#
BRDY#
104 100 10C 108
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