Intel Embedded Intel486, Hardware Reference Manual

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
8-2
8.3 EISA BUS: SYSTEM DESIGN EXAMPLE
8.3.1 Introduction to the EISA Architecture
EISA represents an extension to the Industry Standard Architecture (ISA) but maintains compat-
ibility with ISA expansion boards and software. EISA provides the following important enhance-
ments:
•
32-bit address bus for CPU, DMA and bus masters
•
32-bit data transfers for CPU, DMA, I/O devices and bus masters
•
High speed synchronous bus transfers of 1.5 cycles per doubleword
•
Automatic translation of bus cycles between EISA and ISA master and slaves
•
Up to 33 Mbytes/second transfer rates for bus masters and DMA devices
•
Interrupts are programmable to be edge- or level-sensitive
•
Support of intelligent bus master peripheral controllers
The EISA bus is designed to handle wider address and data buses than those of ISA. All EISA
connector, performance, and function enhancements are a superset to those of ISA. EISA main-
tains full compatibility with ISA expansion boards and software.
Bus masters and multiple processors on the EISA bus can be synchronized to a common clock
for greater performance. Burst cycles can be executed at 33 Mbytes/sec transfer rate and a stan-
dard EISA cycle can transfer data in two cycles. However, CPUs are permitted to generate 1.5-
clock “compressed” cycles for slaves that request such cycles.
EISA systems can support DMA transfers with 32-bit addressability, and with 8-, 16-, or 32-bit
data. 32-bit DMA devices can transfer data at 33 Mbytes/sec using burst cycles.
EISA-based computers support a bus master architecture for intelligent peripherals. The bus mas-
ter provides a high-speed channel with data rates up to 33 Mbytes/sec. The bus master provides
localized intelligence with a dedicated I/O processor and local memory to relieve the host of so-
phisticated memory access functions. Peripherals that use bus mastering techniques include disk
controllers, LAN interfaces, data acquisition systems and certain classes of graphic controllers.
The EISA bus provides a mechanism for data size translation which is useful when it is transfer-
ring data between 16-bit ISA bus masters and 8-bit or 16-bit memory, I/O slaves, or DMA devic-
es. The system board also provides a mechanism for transactions between 16-bit ISA devices and
32-bit EISA devices.
EISA systems provide a centralized arbiter that allows efficient bus sharing between multiple
EISA bus masters and DMA devices. An active bus master or DMA device may be preempted
when another device needs the bus. Further, if a device does not release the bus once it has been
preempted, then the centralized arbiter can reset the device. The EISA arbitration method grants
the bus to the DMA devices, the memory controller for DRAM refreshes, the bus masters, and
the host CPU in an efficient rotational manner. The rotational scheme provides shorter latencies
for DMA devices to ensure compatibility with ISA devices. Bus masters and CPUs have longer
latencies because often they have buffers.