Intel Embedded Intel486, Hardware Reference Manual

Page: 169 / 334

6-19
CACHE SUBSYSTEM
a similar manner, allowing the L2 cache to be implemented into an Intel486 processor system
with ease.
6.8.1 The Memory Hierarchy and Advantages of a Second-level Cache
The Intel486 processor has an on-chip cache and a high-speed register set. These registers are ac-
corded the first level of memory hierarchy. Instructions can be executed in a single clock, and at
an average cycles-per-instruction rate of 1.8 (CPI). The next level of hierarchy is accorded to the
second-level cache, which can consist of one or more L2 cache devices. These sustain a high level
of performance by supporting the fastest possible memory accesses, requiring only two clock cy-
cles for the first read and one clock cycle for each of the subsequent three reads in a burst cycle.
System performance degrades if main memory accesses are required. However, with the on-chip
L1 cache and the external L2 cache, the number of main memory read accesses is reduced con-
siderably.
Figure 6-12 shows the memory hierarchy in a typical Intel486 processor system.
Figure 6-12. Intel486™ Processor System Memory Hierarchy
Because the Intel486 processor internal cache is so efficient, most external CPU bus cycles are
DRAM page misses. An L2 cache improves the bus latency problem, as data is available a large
percentage of the time from the cache for read operations. A large main memory can have an ac-
cess time of six to eight cycles on a page miss. On page hits data can be provided in three or four
cycles.
Intel486™ CPU
Register
File
8 Kbyte
Cache
Main Memory
2
nd
-
Level
Higher
Bandwidth
Main
Memory
High Band
Width
L2 Cache
1
ST
Level Cache
Highest Bandwidth
L2 Cache L2 Cache
L2 Cache
Processor Bus