Intel Embedded Intel486, Hardware Reference Manual

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8-27
SYSTEM BUS DESIGN
PCI bus commands indicate to the target the type of transaction desired by the master. These com-
mands are presented on the C/BE3#–C/BE0# signals during the address phase of a transfer.
Table 8-2 summarizes the system controller’s support of the PCI bus commands.
8.4.3.5 Host to PCI Cycles
Host bus accesses to PCI bus are always in the Host bus address range, as defined by A31–A30,
A26–A2 and the four BE lines. The PCI address lines are driven during the address phase. AD29–
AD27 lines are driven to the value of A30, during Host accesses to PCI.
The system controller has the ability to burst up to 32 back-to-back CPU memory writes on the
PCI bus. This function in controlled by the PCICON register. The system controller is capable of
merging 8/16-bit graphic write cycles to the same dword address into the same posted write buff-
er location (controlled by the PCICON register). The merged data is then driven as a single dword
cycle on the PCI bus. Byte merging is performed in the compatible VGA range only.
8.4.3.6 Exclusive Cycles
The system controller, as a PCI master, never performs LOCKed cycles. The CPU does not return
active HLDA while it is performing a LOCKed sequence. Also, the CPU is the only active mas-
ter, as long as HLDA is inactive. Thus, the system controller does not need to drive LOCK to
Table 8-2. Supported PCI Bus Commands
C/BE[3:0] Command Type
Supported As
Target
Supported As
Master
0000 Interrupt Acknowledge No No
0001 Special Cycle No No
0010 I/O Read Yes Yes
0011 I/O Write Yes Yes
0100 Reserved D D
0101 Reserved D D
0110 Memory Read Yes Yes
0111 Memory Write Yes Yes
1000 Reserved D D
1001 Reserved D D
1010 Configuration Read No Yes
1011 Configuration Write No Yes
1100 Memory Read Multiple Yes
(1)
No
1101 Dual Address Cycle No No
1110 Memory Read Line Yes
(1)
No
1111 Memory Write and Invalidate Yes
(2)
No
NOTES:
1.
As a target, the system controller treats this command as a memory read command.
2. As a target, the system controller treats this command as a memory write command.