Intel Embedded Intel486, Hardware Reference Manual

Page: 219 / 334

7-47
PERIPHERAL SUBSYSTEM
•
Proposed 10BASE-F
•
Proposed 10BASE-T
7.6.1.5 Transmit and Receive Operation
Most of the bus traffic initiated by the coprocessor consists of DMA transfers of frame data. The
coprocessor transmits data as a series of frames by executing a series of high-level commands
from the command list in memory. These commands are fetched by the coprocessor and executed
in parallel with processor operations. A single transmit command contains all the information
necessary to prepare and execute the transmission of one or more data frames.
The data consists of a buffer descriptor and a data buffer containing the actual data. These may
also be chained into a linked list of buffer descriptors and associated data buffers. A frame with
a long data field can therefore be transmitted using several shorter buffers chained together. This
is useful when assembling frames which include nested headers generated by independent soft-
ware modules.
In order for the coprocessor to receive frames, the processor must first dedicate an area of mem-
ory as a receive buffer space and enable the coprocessor for reception. Frames arrive unsolicited
at the coprocessor network interface. The coprocessor must always be prepared to store them in
an buffer area of memory known as the free frame area. The receive frame area is a list of free
frame descriptors and a list of user-prepared buffers. The coprocessor fills the buffers as frames
are received, and it reformats the free buffer list into received frame structures. The frame struc-
ture stored is the same as that for frames to be transmitted. The data contained in the buffers is
transferred by means of the on-chip DMA controller. This allows bidirectional, autonomous
transfer of data blocks partitioned as buffers or chained into frames. Buffers which contain errors
are recovered automatically without processor intervention.
The coprocessor monitors the frames presented on the serial interface for a destination address
which corresponds to its own unique address, one or more multicast addresses, or the broadcast
address. When a match is found, the frame’s destination, source addresses, and length field are
stored, and the data field is placed in the next available buffer. As one buffer is filled, the device
automatically links the next available buffer until the entire frame is stored. This technique ac-
commodates buffer sizes which are much shorter than the maximum permitted frame length.
When a frame has been received without error, several housekeeping tasks are performed by the
coprocessor. If a frame error occurs, the coprocessor re-initializes the DMA pointers and reclaims
any buffers to which the frame had been allocated.
7.6.1.6 Bus Throttle Timers
The 82596 coprocessor’s use of the processor bus is regulated with the coprocessor’s bus throttle
timer logic. These timers are independently programmed and can be triggered internally or exter-
nally. The operation of the timers is shown in
Figure 7-25 . Two timers are associated with the bus
throttle function:
•
TON Timer: Defines the maximum time the coprocessor can remain bus master.
•
TOFF Timer: Defines the minimum time the coprocessor must wait before re-asserting the
HOLD output to request the bus again.