Intel Embedded Intel486, Hardware Reference Manual

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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6.6 CACHE AND DMA OPERATIONS
Some of the issues related to cache consistency in systems employing DMA have already been
covered in the preceding section. Because a DMA controller or other bus master can update main
memory, there is a possibility of stale data in the cache. The problem can be avoided through
snooping, cache transparency, and non-cacheable designs.
In snooping, the cache controller monitors the system address bus and invalidates cache locations
that will be written to during a DMA cycle. This method is advantageous in that the processor
can access its cache during DMA operations to main memory. Only a “snoop hit” causes an in-
validation cycle (or update cycle) to occur.
In cache transparency, memory accesses through the CPU and the DMA controller are directed
through the cache, requiring minimal hardware. However, the main disadvantage is that while a
DMA operation is in progress, the CPU bus is placed in HOLD. The concurrency of CPU/cache
and DMA controller/main memory operations is not supported.
In non-cacheable designs, a separate dual-ported memory can be used as the non-cacheable por-
tion of the memory, and the DMA device is tightly coupled to this memory. In this way, the prob-
lem of stale data cannot occur.
In all of the approaches, the cache should be made software transparent so that DMA cycles do
not require special software programming to ensure cache coherency.
6.7 CACHE FOR SINGLE VERSUS MULTIPLE PROCESSOR SYSTEMS
6.7.1 Cache in Single Processor Systems
In single CPU systems, a write-through cache is an ideal cache solution. Write-through cache
solves consistency issues, may be designed as a plug-in option, and is less expensive. The main
drawback of a write-through cache is its inability to reduce main memory utilization for write cy-
cles. However, this is not as critical a consideration to single CPU designs.
6.7.2 Cache in Multiple Processor Systems
The Intel486 processor is designed for multiple-processor applications. The BREQ output per-
mits a simple hardware interface for bus arbitration. The on-board and second-level caches have
a high hit rate and reduce main memory accesses for reads. Each microprocessor may have its
own local cache or all the microprocessors may share a global cache. With multi-masters, bus uti-
lization is critical. When a write-back cache is used, the bus utilization is reduced compared to a
write-through cache for write operations.
The multi-processor system illustrated in Figure 6-10 shows two processors and a DMA control-
ler that are connected over the system bus. The address bus on the Intel486 processor and the L2
cache controller are bidirectional to allow cache invalidation on system bus memory writes by
other masters. The arbitration logic arbitrates between the processors and the DMA controller.
The CPUs and their second-level cache monitor the system bus to identify cache writes. The sys-
tem must have the mechanisms to support invalidation cycles and to ensure consistency between
the contents of the two caches and memory. Coherency is achieved by snooping the address bus.
When a write is identified by one processor to a location contained in the other's cache, an inval-