Intel Embedded Intel486, Hardware Reference Manual

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
10-24
Figure 10-19. Use of Series Termination to Avoid Impedance Mismatch
10.3.2.2 Daisy Chaining
In laying out printed circuit boards, a stub or T-connection is another source of signal reflection.
These types of connections act as inductive loads in the signal path. In daisy chaining, a single
trace is run from the source, and the loads are distributed along this trace. This is shown in
Figure
10-20 .
Figure 10-20. “Daisy” Chaining
An alternative to this technique is to run multiple traces from the source to each load. Each trace
has unique reflections. These reflections are then transmitted down other traces when they return
to the source. In such cases a separate termination is required for each branch. To eliminate these
T-connections, high-frequency designs are routed as daisy chains.
Along the chain, each gate provides its own impedance load; thus it is necessary to distribute
these loads evenly along the length of the chain. Hence, the impedance along the chain changes
in a series of steps and it is easier to match. The overall speed of this line is faster and predictable.
Also, all loads should be placed at equal distances (regular intervals).
10.3.2.3 90-Degree Angles
Another major cause of reflections are 90-degree angles in the signal paths, which cause an abrupt
change in the signal direction. It promotes signal reflection. For high-frequency layout of designs,
avoid 90-degree trace angles and use 45- or 135-degree trace angles as shown in
Figure 10-21 .
Z
S
= 10
Ω
45.6
Ω
Z
0
= 55.6
Ω
Z
L
= 10 K
Ω
Load
Load Load
Source
. . .