Intel Embedded Intel486, Hardware Reference Manual

Page: 315 / 334

10-31
PHYSICAL DESIGN AND SYSTEM DEBUGGING
a more accurate picture of system loading in high-frequency systems. In addition, it allows new
factors to be considered, such as inductance and the effect of reflections upon the quality of the
signal waveform.
10.5.1 Requirements
The Intel486 processor facilitates an easy-to-implement 1x clock interface. An external, TTL-
compatible 25/33 MHz clock synchronizes both the internal functional blocks of the micropro-
cessors and the external signals. Most of the Intel486 processor’s board logic circuitry also uses
this clock.
The clock input requirements for Intel486 processor systems are more stringent than those for
many commonly used TTL devices, however. The specifications are -0.3 Volts to 0.8 volts for a
logic low and 2.0 volts to V
CC
plus 0.3 volts for a logic high.
The minimum high and low times are specified as 11 ns at 25 MHz and 5 ns at 33 MHz. The typ-
ical clock timings are shown in
Figure 10-24 .
Figure 10-24. Typical Clock Timings
10.5.2 Routing
Achieving the proper clock routing around a 25/33 MHz (or higher) printed circuit board is del-
icate because problems can arise if certain design guidelines are not followed. For example fast
clock edges cause reflections from high impedance terminations. These reflections can cause sig-
nificant signal degradations in the systems operating at 25/33 MHz clock rates. This section cov-
ers some design guidelines for properly laying out the clock lines for efficient Intel486 processor
operation.
Since the rise/fall time of the clock signal is typically in the range of 2-4 ns, the reflections at this
speed could result in undesirable noise and unacceptable signal degradation. The degree of re-
flection depends on the impedance of the trace of the clock connection. These reflections can be
t2
t4
t1
t3
1.5 V
t5
0.8 V
1.5 V
1.5 V
t4
ty
1.5 V
tx
tx = Input Setup Times
ty = Input Hold Times, Output Float, Valid and Hold Times
CLK