Intel Embedded Intel486, Hardware Reference Manual

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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In snooping, cache controllers monitor the bus lines and invalidate any shared locations that are
written by another processor. The common cache location is invalidated and cache consistency
is maintained. This method is shown in
Figure 6-7 .
Figure 6-7. Bus Watching/Snooping for Shared Memory Systems
In broadcasting/hardware transparency, the addresses of all stores are transmitted to all the other
cache so that all copies are updated. This is accomplished by routing the accesses of all devices
to main memory through the same cache. Another method is by copying all cache writes to main
memory and to all of the cache that share main memory. A hardware transparent system is shown
in
Figure 6-8 .
Figure 6-8. Hardware Transparency
In non-cacheable memory systems, all shared memory locations are considered non-cacheable.
In such systems, access to the shared memory is never copied in the cache, and the cache never
Shared
Memory
Cache
Controller
Snoop
Address I/P
Other
Bus Master(s)
CPU
Main
Memory
Cache
Cache CPU
Other
Bus
Master