Intel Embedded Intel486, Hardware Reference Manual

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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Figure 3-6. Segmentation and Paging Address Formats
3.10 PAGING UNIT
The paging unit allows access to data structures larger than the available memory space by keep-
ing them partly in memory and partly on disk. Paging divides the linear address space into
4-Kbyte blocks called pages. Paging uses data structures in memory called page tables for map-
ping a linear address to a physical address. The cache uses physical addresses and puts them on
the processor bus. The paging unit also identifies problems, such as accesses to a page that is not
resident in memory, and raises exceptions called page faults. When a page fault occurs, the oper-
ating system has a chance to bring the required page into memory from disk. If necessary, it can
free space in memory by sending another page out to disk. If paging is not enabled, the physical
address is identical to the linear address.
The paging unit includes a translation lookaside buffer (TLB) that stores the 32 most recently
used page table entries.
Figure 3-7 shows the TLB data structures. The paging unit looks up linear
addresses in the TLB. If the paging unit does not find a linear address in the TLB, the unit gen-
erates requests to fill the TLB with the correct physical address contained in a page table in mem-
ory. Only when the correct page table entry is in the TLB does the bus cycle take place. When the
paging unit maps a page in the linear address space to a page in physical memory, it maps only
the upper 20 bits of the linear address. The lowest 12 bits of the physical address come unchanged
from the linear address.
A5142-01
Segment
Selector
Segment
Offset
0 47 32 31
Logical Address
Page Offset
Page Directory
Offset
Page Table
Offset
0 21 22
11
11 12 31
Linear Address
Page Offset Page Base Address
Translated by the segmentation unit
0 12 31
Physical Address
Translated by the paging unit