Intel Embedded Intel486, Hardware Reference Manual

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INTERNAL ARCHITECTURE
Figure 3-7. Translation Lookaside Buffer
Most programs access only a small number of pages during any short span of time. When this is
true, the pages stay in memory and the address translation information stays in the TLB. In typical
systems, the TLB satisfies 99% of the requests to access the page tables. The TLB uses a pseudo-
LRU algorithm, similar to the cache, as a content-replacement strategy.
The TLB is flushed whenever the page directory base register (CR3) is loaded. Page faults can
occur during either a page directory read or a page table read. The cache can be used to supply
data for the TLB, although this may not be desirable when external logic monitors TLB updates.
Unlike segmentation, paging is invisible to application programs and does not provide the same
kind of protection against programs altering data outside a restricted part of memory. Paging is
visible to the operating system, which uses it to satisfy application program memory require-
ments. For more information on paging and segmentation, see the Embedded Intel486™ Devel-
oper’s Manual.
Way 3 Way 2 Way 1
Data
Block
Way 0 Way 3 Way 2 Way 1
Valid Attribute
and Tag Block
A5174-01
LRU
Block
Way 0
Set 7
Set 6
Set 5
Set 4
Set 3
Set 2
Set 1
Set 0
Physical Address
20 Bits
Data
3 Bits
Tag Attribute
17 Bits 3 Bits 1 Bit
Valid
31 12 31 12 15 14
Linear Address
Set Select