Intel Embedded Intel486, Hardware Reference Manual

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
6-10
Figure 6-5. The Cache Data Organization for the Intel486™ Processor’s On-Chip Cache
6.3.3 Block/Line Size
Block size is an important consideration in cache memory design. Block size is also referred to
as the line size, or the width of the cache data word. The block size may be larger than the word,
and this can impact the performance, because the cache may be fetching and storing more infor-
mation than the CPU needs.
As the block size increases, the number of blocks that fit in the cache is reduced. Because each
block fetch overwrites the older cache contents, some blocks are overwritten shortly after being
fetched. In addition, as block size increases, additional words are fetched with the requested
word. Because of program locality, the additional words are less likely to be needed by the pro-
cessor.
When a cache is refilled with four dwords or eight words on a miss, the performance is dramati-
cally better than a cache size that employs single-word refills. Those extra words that are read
into the cache, because they are subsequent words and because programs are generally sequential
in nature, are likely be hits in subsequent cache accesses. Also, the cache refill algorithm is a sig-
nificant performance factor in systems in which the delay in transferring the first word from the
main memory is long but in which several subsequent words can be transferred in a shorter time.
Word 0 Word 1 Word 2 Word 3
2 Kbytes
Set 0
Set 1
Set 2
Set 3
2 Kbytes
2 Kbytes
2 Kbytes
4-Way Set Associative 8-Kbyte Cache
Line Size = 4 DWORDS
Line Size = 16 Bytes