Intel Embedded Intel486, Hardware Reference Manual

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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these multiprocessor environments. A write-back cache will, however, be more complex in its ar-
chitecture and coherency mechanisms.
6.8 AN Intel486™ PROCESSOR SYSTEM EXAMPLE
A typical Intel486 processor system is shown in Figure 6-11 . The Intel486 processor has a local
bus that consists of address, data and control buses. These buses are either buffered, registered or
latched to comprise the system bus.
Figure 6-11. A Typical Intel486™ Processor System
The memory subsystem is made up of DRAMs, SRAMs, Flash and EPROMs. Main memory ac-
cesses are usually addressed to a DRAM subsystem; however, the I/O subsystem can communi-
cate with the Intel486 processor and with the memory subsystem during DMA operations.
Cache consistency must be maintained whenever main memory accesses occur during DMA op-
erations. Bus snooping and validation logic can monitor the bus to detect memory writes that may
be initiated by other bus masters. If such writes are detected, portions of the processor and the L2
cache may have to be invalidated. The Intel486 processor has mechanisms that can invalidate
cache entries; the L2 cache device should also have this capability.
The typical L2 cache is closely coupled to the Intel486 processor: the address, data, and control
signals are connected to the processor’s local bus, and L2 cache control signals interface to the
system bus as well. The system bus control signals interface to the processor and the L2 cache in
Controls
Controls
Local Bus
Data
Address
Intel486™ CPU Bus
Intel486
CPU
Data
XCVR
Address
XCVR
L2 Cache
Bus Snooping and
Validation Logic
Clock and Reset
Logic
Memory
Subsystem
I/O
Arbitration
Logic
DMA Controller
LAN Controller