Intel Embedded Intel486, Hardware Reference Manual

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4-37
BUS OPERATION
If the system asserts EADS# before the first data in the line fill is returned to the Intel486 proces-
sor, the system must return data consistent with the new data in the external memory upon re-
sumption of the line fill after the invalidation cycle. This is illustrated by the asserted EADS#
signal labeled “1” in
Figure 4-28 .
If the system asserts EADS# at the same time or after the first data in the line fill is returned (in
the same clock that the first RDY# or BRDY# is asserted or any subsequent clock in the line fill)
the data is read into the Intel486 processor input buffers but it is not stored in the on-chip cache.
This is illustrated by asserted EADS# signal labeled “2” in
Figure 4-28 . The stale data is used to
satisfy the request that initiated the cache fill cycle.
Figure 4-28. Cache Invalidation Cycle Concurrent with Line Fill
242202-093
NOTES:
1. Data returned must be consistent if its address equals the invalidation address in this clock.
2. Data returned is not cached if its address equals the invalidation address in this clock.
CLK
ADS#
ADDR
AHOLD
RDY#
DATA
Ti T1 T2 T2 T2 T2 T2 T2 Ti
To Processor
EADS#
1 2
BRDY#
KEN#
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