Intel Embedded Intel486, Hardware Reference Manual

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4-1
CHAPTER 4
BUS OPERATION
All Intel486™ processors operate in Standard Bus (write-through) mode. However, when the in-
ternal cache of the Write-Back Enhanced IntelDX4™ processor is configured in write-back
mode, the processor bus operates in the Enhanced Bus mode, which is described in
Section 4.4 .
When the internal cache of the Write-Back Enhanced IntelDX4 processor is configured in write-
through mode, the processor bus operates in Standard Bus mode, identical to the other embedded
Intel486 processors.
4.1 DATA TRANSFER MECHANISM
All data transfers occur as a result of one or more bus cycles. Logical data operands of byte, word
and doubleword lengths may be transferred without restrictions on physical address alignment.
Data may be accessed at any byte boundary but two or three cycles may be required for unaligned
data transfers. (See
Section 4.1.2, “Dynamic Data Bus Sizing,” and Section 4.1.5, “Operand
Alignment.” )
The Intel486 processor address signals are split into two components. High-order address bits are
provided by the address lines, A31–A2. The byte enables, BE3#–BE0#, form the low-order ad-
dress and provide linear selects for the four bytes of the 32-bit address bus.
The byte enable outputs are asserted when their associated data bus bytes are involved with the
present bus cycle, as listed in
Table 4-1 . Byte enable patterns that have a deasserted byte enable
separating two or three asserted byte enables never occur (see Table 4-5 on page 4-7 ). All other
byte enable patterns are possible.
Address bits A0 and A1 of the physical operand's base address can be created when necessary.
Use of the byte enables to create A0 and A1 is shown in
Table 4-2 . The byte enables can also be
decoded to generate BLE# (byte low enable) and BHE# (byte high enable). These signals are
needed to address 16-bit memory systems. (See
Section 4.1.3, “Interfacing with 8-, 16-, and 32-
Bit Memories.” )
4.1.1 Memory and I/O Spaces
Bus cycles may access physical memory space or I/O space. Peripheral devices in the system can
be either memory-mapped, I/O-mapped, or both. Physical memory addresses range from
Table 4-1. Byte Enables and Associated Data and Operand Bytes
Byte Enable Signal Associated Data Bus Signals
BE0# D7–D0 (byte 0–least significant)
BE1# D15–D8 (byte 1)
BE2# D23–D16 (byte 2)
BE3# D31–D24 (byte 3–most significant)