Intel Embedded Intel486, Hardware Reference Manual

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6-3
CACHE SUBSYSTEM
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Associativity (discussed in Section 6.2.2, “Why Add an External Cache?” ): Increased
associativity increases the cache hit rate but also increases its complexity and reduces its
speed.
•
Line Size: The amount of data the cache must fetch during each cache line replacement
(every miss) affects performance. More data takes more time to fill a cache line, but then
more data is available and the hit rate increases.
•
Write-Back and Write Posting: The ability to write quickly to the cache and have the cache
then write to the slower memory increases performance. Implementing these types of cache
designs can be very complex, however.
•
Features: Adding features such as write-protection (to be able to cache ROM memory), bus
watching, and multiprocessing protocols can speed a cache but increases cost and
complexity.
•
Speed: Not all cache return data to the CPU as quickly as possible. It is less expensive and
complex to use slower cache memories and cache logic.
6.3.1 Cache Size and Performance
Hit rates for various first-level cache configurations are shown in Table 6-1 . These statistics are
conservative because they illustrate the lowest hit rates generated by analyzing several main-
frame traces. The hit rates are not absolute quantities, and the hit rate of a particular configuration
is software-dependent. However, the table allows a meaningful comparison of the various cache
configurations. It also indicates the degree of hardware complexity needed to arrive at a particular
cache efficiency.
Table 6-1 presents direct-mapped, 2-way, and 4-way set associative cache,
which are all discussed in the next section.
Table 6-1. Level-1 Cache Hit Rates (Sheet 1 of 2)
Cache Configurations
Hit Rate
Size Associativity Line Size
1 Kbyte direct 4 bytes 41%
8 Kbyte direct 4 bytes 73%
16 Kbyte direct 4 bytes 81%
32 Kbyte direct 4 bytes 86%