FPGA Configuration
To avoid configuration failures, the Intel Agilex device requires additional clocks for transceivers, HPS EMIF IP, and all E-tile
variants. You must provide a free-running, stable reference clock to these blocks before configuration begins. The clock
frequencies must match the frequency settings specified in the Intel Quartus Prime software during configuration. This
reference clock is in addition to the configuration clock requirements for an internal or external oscillator described in
on page 49.
These blocks and their specific clock names are as listed below.
•
HPS reference clock:
HPS_OSC_CLK
, when HPS enabled
(
)
•
HPS EMIF:
pll_ref_clk
•
E-tile transceivers:
REFCLK_GXE
•
R-tile transceivers:
REFCLK_GXR
Note:
The transceiver power supplies must be at nominal levels for successful configuration. You can use the V
CC
and V
CCP
power
supplies for limited transceiver channel testing. Designs that include many transceivers require an auxiliary power supply to
operate reliably.
Intel Quartus Prime Pro Edition software allows you to configure the HPS prior to FPGA configuration. To enable this option,
select HPS First in the Assignments
➤
Device
➤
Device and Pin Options
➤
Configuration
➤
HPS/FPGA
Configuration order dialog box.
HPS First Configuration
Intel Agilex devices have the option of booting the HPS before configuring the FPGA core logic. This method is known as the
HPS first configuration. When you choose this option in the Intel Quartus Prime Pro Edition software, the following clocks must
be operational prior to the FPGA I/O, HPS I/O, and HPS boot, also called a phase 1 configuration:
•
HPS reference clock:
HPS_OSC_CLK
•
HPS EMIF (when in use):
pll_ref_clk
•
E-tile transceivers:
REFCLK_GXE
(3)
If you use the FPGA to HPS free clock as the HPS PLL reference clock, the
HPS_OSC_CLK
clock may not be required.
(4)
The reference clock must be on when you want to reconfigure the device.
2. Intel Agilex Configuration Details
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
27
