2.5.3.5. Specifying Pins for Partial Reconfiguration (PR)
The partial reconfiguration signals use GPIO pins.
The following signals control partial reconfiguration in Intel Agilex devices:
•
PR_REQUEST
•
PR_READY
•
PR_ERROR
•
PR_DONE
Connect these partial reconfiguration signals to the Partial Reconfiguration External Configuration Controller Intel FPGA IP.
Related Information
Creating a Partial Reconfiguration Design
2.6. Configuration Clocks
2.6.1. Setting Configuration Clock Source
You must specify the configuration clock source by selecting either the internal oscillator or
OSC_CLK_1
with the supported
frequency. By default, the SDM uses the internal oscillator for device configuration. Specify an
OSC_CLK_1
clock source for
the fastest configuration time.
Complete the following steps to select the configuration clock source:
1. To specify OSC_CLK_1 as the clock source, on the Assignments menu, click Device.
2. In the Device and Pin Options dialog box, select the General category.
3. Specify the configuration clock source from the Configuration clock source drop down menu.
2. Intel Agilex Configuration Details
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
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