9. Document Revision History for the Intel Agilex Configuration User Guide
Document Version
Intel Quartus
Prime Version
Changes
2021.10.29
21.3
Made the following changes:
• Removed the Configuration Pins I/O Standard, Drive Strength, and IBIS Model section.
— Replaced content with a section listing the I/O standards and features for configuration pins in different configuration
schemes.
— Added IBIS Model.
• Revised the Power-On, Configuration, and Reconfiguration Timing Diagram figure.
• Added text about I/O pins in SDM and HPS banks in Configuration Flow Diagram.
• Added note about valid
nSTATUS
response in Intel Agilex Configuration Timing Diagram and The AVST_READY Signal
sections.
2021.10.04
21.3
Made the following changes:
• Added R-tile transceiver clock requirement in Additional Clock Requirements for HPS and Transceivers
• Updated
MSEL
in the MSEL Pull-Up and Pull-Down Circuit Diagram figure.
• Updated SDM I/O Pins for Power Management and SmartVID:
— Replaced ISL82XX with LTC3888 device
— Added Page Command setting description
• Corrected the maximum size of the first bitstream section value in OSC_CLK_1 Requirements. The maximum size is 512
KB.
• Added new topic: Generating Compressed SOF File
• Renamed the Compact Flash Memory to the External Non-Volatile Flash Memory in the following figures:
— Connections for Avalon-ST x8 Single-Device Configuration
— Connections for Avalon-ST x16 Single-Device Configuration
— Connections for Avalon-ST x32 Single-Device Configuration
• Globally added R
UP
registers description in the AS and JTAG-related figures.
• Updated IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core. Added note
about PFL II IP maximum throughput.
• Added guidance about JTAG configuration failure in the Debugging Guidelines for the JTAG Configuration Scheme.
continued...
683673 | 2021.10.29
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