3.1.7.1.1. Generating and Programming a .pof into CFI Flash
The Intel Quartus Prime software generates the
.sof
when you compile your design. You use the
.sof
to generate the
.pof
.
This process includes the following steps:
1. Generating a
.pof
for the PFL II IP using the Intel Quartus Prime File
➤
Programming File Generator.
2. Using the Intel Quartus Prime Programmer to write the Intel Agilex device
.pof
to the flash device.
Figure 20.
Programming the CFI Flash Memory with the JTAG Interface
External
Host
CFI Flash
Memory
Configuration Data
Common
Flash
Interface
PFL II
Quartus Prime
Software
using JTAG
The PFL II IP core supports dual flash memory devices in burst read mode to achieve faster configuration times. You can
connect two MT28EW CFI flash memory devices to the host in parallel using the same data bus, clock, and control signals.
Intel does not support connecting two of non-MT28W CFI flash memory devices to PFL II IP core in parallel. During FPGA
configuration, the
AVST_CLK
frequency is four times faster than the
flash_clk
frequency.
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
66
